From b3a148b22f163d1a9ad3bca36dc3f18b1988c738 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Mon, 10 Jan 2022 15:29:01 -0600 Subject: [PATCH] soc: rt11xx: Enable ethernet clocks Enable clocks for ethernet module. Signed-off-by: Daniel DeGrasse --- soc/arm/nxp_imx/rt/Kconfig.soc | 4 ++++ soc/arm/nxp_imx/rt/soc_rt11xx.c | 19 ++++++++++++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/soc/arm/nxp_imx/rt/Kconfig.soc b/soc/arm/nxp_imx/rt/Kconfig.soc index 1708fbdd369..698aedca26f 100644 --- a/soc/arm/nxp_imx/rt/Kconfig.soc +++ b/soc/arm/nxp_imx/rt/Kconfig.soc @@ -294,6 +294,7 @@ config SOC_MIMXRT1176_CM7 select HAS_MCUX_PWM select HAS_MCUX_USDHC1 select HAS_MCUX_USDHC2 + select HAS_MCUX_ENET config SOC_MIMXRT1176_CM4 bool "SOC_MIMXRT1176_CM4" @@ -317,6 +318,7 @@ config SOC_MIMXRT1176_CM4 select HAS_MCUX_PWM select HAS_MCUX_USDHC1 select HAS_MCUX_USDHC2 + select HAS_MCUX_ENET config SOC_MIMXRT1166_CM7 bool "SOC_MIMXRT1166_CM7" @@ -347,6 +349,7 @@ config SOC_MIMXRT1166_CM7 select HAS_MCUX_PWM select HAS_MCUX_USDHC1 select HAS_MCUX_USDHC2 + select HAS_MCUX_ENET config SOC_MIMXRT1166_CM4 @@ -371,6 +374,7 @@ config SOC_MIMXRT1166_CM4 select HAS_MCUX_PWM select HAS_MCUX_USDHC1 select HAS_MCUX_USDHC2 + select HAS_MCUX_ENET endchoice diff --git a/soc/arm/nxp_imx/rt/soc_rt11xx.c b/soc/arm/nxp_imx/rt/soc_rt11xx.c index 3cf5d17d3e7..2da45050e20 100644 --- a/soc/arm/nxp_imx/rt/soc_rt11xx.c +++ b/soc/arm/nxp_imx/rt/soc_rt11xx.c @@ -247,7 +247,11 @@ static ALWAYS_INLINE void clock_init(void) CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); /* Init System Pll2 pfd3. */ +#ifdef CONFIG_ETH_MCUX + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 24); +#else CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); +#endif /* Init Sys Pll3. */ CLOCK_InitSysPll3(); @@ -290,7 +294,13 @@ static ALWAYS_INLINE void clock_init(void) #endif /* Configure BUS using SYS_PLL3_CLK */ -#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) +#ifdef CONFIG_ETH_MCUX + /* Configure root bus clock at 198M */ + rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); +#elif defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) + /* Keep root bus clock at default 240M */ rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out; rootCfg.div = 2; CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); @@ -355,6 +365,13 @@ static ALWAYS_INLINE void clock_init(void) CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg); #endif + +#ifdef CONFIG_ETH_MCUX + rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg); +#endif + #ifdef CONFIG_SPI_MCUX_LPSPI /* Configure lpspi using Osc48MDiv2 */ rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;