soc: silabs_exx32: Enable mpu on efr32mg soc

Enables the arm v7m mpu on the efr32mg soc and the board
efr32mg_sltb004a.

Tested on hardware with samples/mpu/mpu_test and
tests/kernel/mem_protect

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
This commit is contained in:
Christian Taedcke 2019-11-05 16:46:34 +01:00 committed by Kumar Gala
commit b25569ef74
7 changed files with 97 additions and 1 deletions

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@ -59,6 +59,8 @@ The efr32mg_sltb004a board configuration supports the following hardware feature
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| MPU | on-chip | memory protection unit |
+-----------+------------+-------------------------------------+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |

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@ -1,6 +1,7 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_ARM_MPU=y
CONFIG_SOC_FAMILY_EXX32=y
CONFIG_SOC_SERIES_EFR32MG12P=y
CONFIG_BOARD_EFR32MG_SLTB004A=y

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@ -3,3 +3,5 @@
zephyr_sources(soc.c soc_gpio.c)
zephyr_sources_ifdef(CONFIG_SYS_POWER_MANAGEMENT soc_power.c)
zephyr_sources_ifdef(CONFIG_ARM_MPU arm_mpu_regions.c)

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@ -0,0 +1,55 @@
/*
* Copyright (c) 2017 Linaro Limited.
* Copyright (c) 2019 Christian Taedcke <hacking@taedcke.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ARM_MPU_MEM_CFG_H_
#define _ARM_MPU_MEM_CFG_H_
#include <soc.h>
#include <arch/arm/cortex_m/mpu/arm_mpu.h>
/* Flash Region Definitions */
#if CONFIG_FLASH_SIZE == 64
#define REGION_FLASH_SIZE REGION_64K
#elif CONFIG_FLASH_SIZE == 128
#define REGION_FLASH_SIZE REGION_128K
#elif CONFIG_FLASH_SIZE == 256
#define REGION_FLASH_SIZE REGION_256K
#elif CONFIG_FLASH_SIZE == 512
#define REGION_FLASH_SIZE REGION_512K
#elif CONFIG_FLASH_SIZE == 1024
#define REGION_FLASH_SIZE REGION_1M
#elif CONFIG_FLASH_SIZE == 2048
#define REGION_FLASH_SIZE REGION_2M
#else
#error "Unsupported configuration"
#endif
/* SRAM Region Definitions */
#if CONFIG_SRAM_SIZE == 16
#define REGION_SRAM_0_SIZE REGION_16K
#elif CONFIG_SRAM_SIZE == 32
#define REGION_SRAM_0_SIZE REGION_32K
#elif CONFIG_SRAM_SIZE == 64
#define REGION_SRAM_0_SIZE REGION_64K
#elif CONFIG_SRAM_SIZE == 128
#define REGION_SRAM_0_SIZE REGION_128K
#elif CONFIG_SRAM_SIZE == 192
#define REGION_SRAM_0_SIZE REGION_128K
#define REGION_SRAM_1_START 0x20000
#define REGION_SRAM_1_SIZE REGION_64K
#elif CONFIG_SRAM_SIZE == 256
#define REGION_SRAM_0_SIZE REGION_256K
#elif CONFIG_SRAM_SIZE == 384
#define REGION_SRAM_0_SIZE REGION_256K
#define REGION_SRAM_1_START 0x40000
#define REGION_SRAM_1_SIZE REGION_128K
#elif CONFIG_SRAM_SIZE == 512
#define REGION_SRAM_0_SIZE REGION_512K
#else
#error "Unsupported configuration"
#endif
#endif /* _ARM_MPU_MEM_CFG_H_ */

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@ -0,0 +1,33 @@
/*
* Copyright (c) 2017 Linaro Limited.
* Copyright (c) 2019 Christian Taedcke <hacking@taedcke.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <arch/arm/cortex_m/mpu/arm_mpu.h>
#include "arm_mpu_mem_cfg.h"
static const struct arm_mpu_region mpu_regions[] = {
/* Region 0 */
MPU_REGION_ENTRY("FLASH_0",
CONFIG_FLASH_BASE_ADDRESS,
REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
/* Region 1 */
MPU_REGION_ENTRY("RAM_0",
CONFIG_SRAM_BASE_ADDRESS,
REGION_RAM_ATTR(REGION_SRAM_0_SIZE)),
/* Region 2 */
#ifdef REGION_SRAM_1_SIZE
MPU_REGION_ENTRY("RAM_1",
(CONFIG_SRAM_BASE_ADDRESS + REGION_SRAM_1_START),
REGION_RAM_ATTR(REGION_SRAM_1_SIZE)),
#endif
};
const struct arm_mpu_config mpu_config = {
.num_regions = ARRAY_SIZE(mpu_regions),
.mpu_regions = mpu_regions,
};

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@ -7,6 +7,7 @@ config SOC_SERIES_EFR32MG12P
bool "EFR32MG12P Series MCU"
select CPU_CORTEX_M4
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select SOC_FAMILY_EXX32
select HAS_SILABS_GECKO
select HAS_SWO

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@ -18,7 +18,9 @@
#ifndef _ASMLANGUAGE
#include <em_common.h>
#include <device.h>
/* Add include for DTS generated information */
#include <generated_dts_board.h>
#include "soc_pinmap.h"
#include "../common/soc_gpio.h"