dts: add i.MX 943 Cortex-A Core dts
Added i.MX 943 Cortex-A Core dts file and clock binding header file. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
This commit is contained in:
Jiafei Pan
Anas Nashif
parent
c0aee5c224
commit
b0ba009d4d
2 changed files with 531 additions and 0 deletions
247
dts/arm64/nxp/nxp_mimx943_a55.dtsi
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247
dts/arm64/nxp/nxp_mimx943_a55.dtsi
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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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#include <arm64/armv8-a.dtsi>
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#include <zephyr/dt-bindings/clock/imx943_clock.h>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x200>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x300>;
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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};
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gic: interrupt-controller@48000000 {
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0x48000000 0x10000>, /* GIC Dist */
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<0x48060000 0xc0000>; /* GICR (RD_base + SGI_base) */
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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scmi_shmem0: memory@445b1000 {
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compatible = "arm,scmi-shmem";
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reg = <0x445b1000 0x80>;
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};
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};
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firmware {
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scmi {
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compatible = "arm,scmi";
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shmem = <&scmi_shmem0>;
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mboxes = <&mu2 0>;
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mbox-names = "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_clk: protocol@14 {
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compatible = "arm,scmi-clock";
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi_iomuxc: protocol@19 {
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compatible = "arm,scmi-pinctrl";
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reg = <0x19>;
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pinctrl: pinctrl {
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compatible = "nxp,imx943-pinctrl", "nxp,imx93-pinctrl";
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};
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};
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};
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};
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lpuart3: serial@42570000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42570000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART3>;
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status = "disabled";
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};
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lpuart4: serial@42580000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42580000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART4>;
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status = "disabled";
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};
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lpuart5: serial@42590000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42590000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART5>;
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status = "disabled";
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};
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lpuart6: serial@425a0000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x425a0000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART6>;
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status = "disabled";
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};
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lpuart7: serial@42690000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42690000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART7>;
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status = "disabled";
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};
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lpuart8: serial@426a0000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x426a0000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART8>;
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status = "disabled";
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};
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lpuart9: serial@42a50000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42a50000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART9>;
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status = "disabled";
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};
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lpuart10: serial@42a60000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42a60000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART10>;
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status = "disabled";
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};
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lpuart11: serial@42a70000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42a70000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART11>;
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status = "disabled";
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};
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lpuart12: serial@42a80000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42a80000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART12>;
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status = "disabled";
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};
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mu1: mbox@44220000 {
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compatible = "nxp,mbox-imx-mu";
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reg = <0x44220000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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rx-channels = <4>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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lpuart1: serial@44380000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x44380000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART1>;
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status = "disabled";
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};
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lpuart2: serial@44390000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x44390000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART2>;
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status = "disabled";
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};
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mu2: mbox@445b0000 {
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compatible = "nxp,mbox-imx-mu";
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reg = <0x445b0000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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rx-channels = <4>;
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#mbox-cells = <1>;
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};
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mu3: mbox@445d0000 {
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compatible = "nxp,mbox-imx-mu";
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reg = <0x445d0000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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rx-channels = <4>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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mu4: mbox@445f0000 {
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compatible = "nxp,mbox-imx-mu";
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reg = <0x445f0000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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rx-channels = <4>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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};
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284
include/zephyr/dt-bindings/clock/imx943_clock.h
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284
include/zephyr/dt-bindings/clock/imx943_clock.h
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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX943_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX943_CLOCK_H_
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#define IMX943_CLK_32K 1
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#define IMX943_CLK_24M 2
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#define IMX943_CLK_FRO 3
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#define IMX943_CLK_SYSPLL1_VCO 4
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#define IMX943_CLK_SYSPLL1_PFD0_UNGATED 5
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#define IMX943_CLK_SYSPLL1_PFD0 6
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#define IMX943_CLK_SYSPLL1_PFD0_DIV2 7
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#define IMX943_CLK_SYSPLL1_PFD1_UNGATED 8
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#define IMX943_CLK_SYSPLL1_PFD1 9
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#define IMX943_CLK_SYSPLL1_PFD1_DIV2 10
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#define IMX943_CLK_SYSPLL1_PFD2_UNGATED 11
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#define IMX943_CLK_SYSPLL1_PFD2 12
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#define IMX943_CLK_SYSPLL1_PFD2_DIV2 13
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#define IMX943_CLK_AUDIOPLL1_VCO 14
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#define IMX943_CLK_AUDIOPLL1 15
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#define IMX943_CLK_AUDIOPLL2_VCO 16
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#define IMX943_CLK_AUDIOPLL2 17
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#define IMX943_CLK_RESERVED18 18
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#define IMX943_CLK_RESERVED19 19
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#define IMX943_CLK_RESERVED20 20
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#define IMX943_CLK_RESERVED21 21
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#define IMX943_CLK_RESERVED22 22
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#define IMX943_CLK_RESERVED23 23
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#define IMX943_CLK_ENCPLL_VCO 24
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#define IMX943_CLK_ENCPLL_PFD0_UNGATED 25
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#define IMX943_CLK_ENCPLL_PFD0 26
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#define IMX943_CLK_ENCPLL_PFD1_UNGATED 27
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#define IMX943_CLK_ENCPLL_PFD1 28
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#define IMX943_CLK_ARMPLL_VCO 29
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#define IMX943_CLK_ARMPLL_PFD0_UNGATED 30
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#define IMX943_CLK_ARMPLL_PFD0 31
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#define IMX943_CLK_ARMPLL_PFD1_UNGATED 32
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#define IMX943_CLK_ARMPLL_PFD1 33
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#define IMX943_CLK_ARMPLL_PFD2_UNGATED 34
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#define IMX943_CLK_ARMPLL_PFD2 35
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#define IMX943_CLK_ARMPLL_PFD3_UNGATED 36
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#define IMX943_CLK_ARMPLL_PFD3 37
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#define IMX943_CLK_DRAMPLL_VCO 38
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#define IMX943_CLK_DRAMPLL 39
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#define IMX943_CLK_HSIOPLL_VCO 40
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#define IMX943_CLK_HSIOPLL 41
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#define IMX943_CLK_LDBPLL_VCO 42
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#define IMX943_CLK_LDBPLL 43
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#define IMX943_CLK_EXT1 44
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#define IMX943_CLK_EXT2 45
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#define IMX943_CCM_NUM_CLK_SRC 46
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#define IMX943_CLK_ADC (IMX943_CCM_NUM_CLK_SRC + 0)
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#define IMX943_CLK_BUSAON (IMX943_CCM_NUM_CLK_SRC + 1)
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#define IMX943_CLK_CAN1 (IMX943_CCM_NUM_CLK_SRC + 2)
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#define IMX943_CLK_GLITCHFILTER (IMX943_CCM_NUM_CLK_SRC + 3)
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#define IMX943_CLK_GPT1 (IMX943_CCM_NUM_CLK_SRC + 4)
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#define IMX943_CLK_I3C1SLOW (IMX943_CCM_NUM_CLK_SRC + 5)
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#define IMX943_CLK_LPI2C1 (IMX943_CCM_NUM_CLK_SRC + 6)
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#define IMX943_CLK_LPI2C2 (IMX943_CCM_NUM_CLK_SRC + 7)
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#define IMX943_CLK_LPSPI1 (IMX943_CCM_NUM_CLK_SRC + 8)
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#define IMX943_CLK_LPSPI2 (IMX943_CCM_NUM_CLK_SRC + 9)
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#define IMX943_CLK_LPTMR1 (IMX943_CCM_NUM_CLK_SRC + 10)
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#define IMX943_CLK_LPUART1 (IMX943_CCM_NUM_CLK_SRC + 11)
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#define IMX943_CLK_LPUART2 (IMX943_CCM_NUM_CLK_SRC + 12)
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#define IMX943_CLK_M33 (IMX943_CCM_NUM_CLK_SRC + 13)
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#define IMX943_CLK_M33SYSTICK (IMX943_CCM_NUM_CLK_SRC + 14)
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#define IMX943_CLK_PDM (IMX943_CCM_NUM_CLK_SRC + 15)
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#define IMX943_CLK_SAI1 (IMX943_CCM_NUM_CLK_SRC + 16)
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#define IMX943_CLK_TPM2 (IMX943_CCM_NUM_CLK_SRC + 17)
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#define IMX943_CLK_A55 (IMX943_CCM_NUM_CLK_SRC + 18)
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#define IMX943_CLK_A55MTRBUS (IMX943_CCM_NUM_CLK_SRC + 19)
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#define IMX943_CLK_A55PERIPH (IMX943_CCM_NUM_CLK_SRC + 20)
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#define IMX943_CLK_DRAMALT (IMX943_CCM_NUM_CLK_SRC + 21)
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#define IMX943_CLK_DRAMAPB (IMX943_CCM_NUM_CLK_SRC + 22)
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#define IMX943_CLK_DISPAPB (IMX943_CCM_NUM_CLK_SRC + 23)
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#define IMX943_CLK_DISPAXI (IMX943_CCM_NUM_CLK_SRC + 24)
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#define IMX943_CLK_DISPPIX (IMX943_CCM_NUM_CLK_SRC + 25)
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#define IMX943_CLK_HSIOACSCAN480M (IMX943_CCM_NUM_CLK_SRC + 26)
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#define IMX943_CLK_HSIOACSCAN80M (IMX943_CCM_NUM_CLK_SRC + 27)
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#define IMX943_CLK_HSIO (IMX943_CCM_NUM_CLK_SRC + 28)
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#define IMX943_CLK_HSIOPCIEAUX (IMX943_CCM_NUM_CLK_SRC + 29)
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#define IMX943_CLK_HSIOPCIETEST160M (IMX943_CCM_NUM_CLK_SRC + 30)
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#define IMX943_CLK_HSIOPCIETEST400M (IMX943_CCM_NUM_CLK_SRC + 31)
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#define IMX943_CLK_HSIOPCIETEST500M (IMX943_CCM_NUM_CLK_SRC + 32)
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#define IMX943_CLK_SIOPCIETEST50M (IMX943_CCM_NUM_CLK_SRC + 33)
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#define IMX943_CLK_SIOPCIETEST60M (IMX943_CCM_NUM_CLK_SRC + 34)
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#define IMX943_CLK_BUSM70 (IMX943_CCM_NUM_CLK_SRC + 35)
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#define IMX943_CLK_M70 (IMX943_CCM_NUM_CLK_SRC + 36)
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#define IMX943_CLK_M70SYSTICK (IMX943_CCM_NUM_CLK_SRC + 37)
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#define IMX943_CLK_BUSM71 (IMX943_CCM_NUM_CLK_SRC + 38)
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#define IMX943_CLK_M71 (IMX943_CCM_NUM_CLK_SRC + 39)
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#define IMX943_CLK_M71SYSTICK (IMX943_CCM_NUM_CLK_SRC + 40)
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#define IMX943_CLK_BUSNETCMIX (IMX943_CCM_NUM_CLK_SRC + 41)
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#define IMX943_CLK_ECAT (IMX943_CCM_NUM_CLK_SRC + 42)
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#define IMX943_CLK_ENET (IMX943_CCM_NUM_CLK_SRC + 43)
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#define IMX943_CLK_ENETPHYTEST200M (IMX943_CCM_NUM_CLK_SRC + 44)
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#define IMX943_CLK_ENETPHYTEST500M (IMX943_CCM_NUM_CLK_SRC + 45)
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#define IMX943_CLK_ENETPHYTEST667M (IMX943_CCM_NUM_CLK_SRC + 46)
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#define IMX943_CLK_ENETREF (IMX943_CCM_NUM_CLK_SRC + 47)
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#define IMX943_CLK_ENETTIMER1 (IMX943_CCM_NUM_CLK_SRC + 48)
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#define IMX943_CLK_ENETTIMER2 (IMX943_CCM_NUM_CLK_SRC + 49)
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#define IMX943_CLK_ENETTIMER3 (IMX943_CCM_NUM_CLK_SRC + 50)
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#define IMX943_CLK_FLEXIO3 (IMX943_CCM_NUM_CLK_SRC + 51)
|
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#define IMX943_CLK_FLEXIO4 (IMX943_CCM_NUM_CLK_SRC + 52)
|
||||
#define IMX943_CLK_M33SYNC (IMX943_CCM_NUM_CLK_SRC + 53)
|
||||
#define IMX943_CLK_M33SYNCSYSTICK (IMX943_CCM_NUM_CLK_SRC + 54)
|
||||
#define IMX943_CLK_MAC0 (IMX943_CCM_NUM_CLK_SRC + 55)
|
||||
#define IMX943_CLK_MAC1 (IMX943_CCM_NUM_CLK_SRC + 56)
|
||||
#define IMX943_CLK_MAC2 (IMX943_CCM_NUM_CLK_SRC + 57)
|
||||
#define IMX943_CLK_MAC3 (IMX943_CCM_NUM_CLK_SRC + 58)
|
||||
#define IMX943_CLK_MAC4 (IMX943_CCM_NUM_CLK_SRC + 59)
|
||||
#define IMX943_CLK_MAC5 (IMX943_CCM_NUM_CLK_SRC + 60)
|
||||
#define IMX943_CLK_NOCAPB (IMX943_CCM_NUM_CLK_SRC + 61)
|
||||
#define IMX943_CLK_NOC (IMX943_CCM_NUM_CLK_SRC + 62)
|
||||
#define IMX943_CLK_NPUAPB (IMX943_CCM_NUM_CLK_SRC + 63)
|
||||
#define IMX943_CLK_NPU (IMX943_CCM_NUM_CLK_SRC + 64)
|
||||
#define IMX943_CLK_CCMCKO1 (IMX943_CCM_NUM_CLK_SRC + 65)
|
||||
#define IMX943_CLK_CCMCKO2 (IMX943_CCM_NUM_CLK_SRC + 66)
|
||||
#define IMX943_CLK_CCMCKO3 (IMX943_CCM_NUM_CLK_SRC + 67)
|
||||
#define IMX943_CLK_CCMCKO4 (IMX943_CCM_NUM_CLK_SRC + 68)
|
||||
#define IMX943_CLK_BISS (IMX943_CCM_NUM_CLK_SRC + 69)
|
||||
#define IMX943_CLK_BUSWAKEUP (IMX943_CCM_NUM_CLK_SRC + 70)
|
||||
#define IMX943_CLK_CAN2 (IMX943_CCM_NUM_CLK_SRC + 71)
|
||||
#define IMX943_CLK_CAN3 (IMX943_CCM_NUM_CLK_SRC + 72)
|
||||
#define IMX943_CLK_CAN4 (IMX943_CCM_NUM_CLK_SRC + 73)
|
||||
#define IMX943_CLK_CAN5 (IMX943_CCM_NUM_CLK_SRC + 74)
|
||||
#define IMX943_CLK_ENDAT21 (IMX943_CCM_NUM_CLK_SRC + 75)
|
||||
#define IMX943_CLK_ENDAT22 (IMX943_CCM_NUM_CLK_SRC + 76)
|
||||
#define IMX943_CLK_ENDAT31FAST (IMX943_CCM_NUM_CLK_SRC + 77)
|
||||
#define IMX943_CLK_ENDAT31SLOW (IMX943_CCM_NUM_CLK_SRC + 78)
|
||||
#define IMX943_CLK_FLEXIO1 (IMX943_CCM_NUM_CLK_SRC + 79)
|
||||
#define IMX943_CLK_FLEXIO2 (IMX943_CCM_NUM_CLK_SRC + 80)
|
||||
#define IMX943_CLK_GPT2 (IMX943_CCM_NUM_CLK_SRC + 81)
|
||||
#define IMX943_CLK_GPT3 (IMX943_CCM_NUM_CLK_SRC + 82)
|
||||
#define IMX943_CLK_GPT4 (IMX943_CCM_NUM_CLK_SRC + 83)
|
||||
#define IMX943_CLK_HIPERFACE1 (IMX943_CCM_NUM_CLK_SRC + 84)
|
||||
#define IMX943_CLK_HIPERFACE1SYNC (IMX943_CCM_NUM_CLK_SRC + 85)
|
||||
#define IMX943_CLK_HIPERFACE2 (IMX943_CCM_NUM_CLK_SRC + 86)
|
||||
#define IMX943_CLK_HIPERFACE2SYNC (IMX943_CCM_NUM_CLK_SRC + 87)
|
||||
#define IMX943_CLK_I3C2SLOW (IMX943_CCM_NUM_CLK_SRC + 88)
|
||||
#define IMX943_CLK_LPI2C3 (IMX943_CCM_NUM_CLK_SRC + 89)
|
||||
#define IMX943_CLK_LPI2C4 (IMX943_CCM_NUM_CLK_SRC + 90)
|
||||
#define IMX943_CLK_LPI2C5 (IMX943_CCM_NUM_CLK_SRC + 91)
|
||||
#define IMX943_CLK_LPI2C6 (IMX943_CCM_NUM_CLK_SRC + 92)
|
||||
#define IMX943_CLK_LPI2C7 (IMX943_CCM_NUM_CLK_SRC + 93)
|
||||
#define IMX943_CLK_LPI2C8 (IMX943_CCM_NUM_CLK_SRC + 94)
|
||||
#define IMX943_CLK_LPSPI3 (IMX943_CCM_NUM_CLK_SRC + 95)
|
||||
#define IMX943_CLK_LPSPI4 (IMX943_CCM_NUM_CLK_SRC + 96)
|
||||
#define IMX943_CLK_LPSPI5 (IMX943_CCM_NUM_CLK_SRC + 97)
|
||||
#define IMX943_CLK_LPSPI6 (IMX943_CCM_NUM_CLK_SRC + 98)
|
||||
#define IMX943_CLK_LPSPI7 (IMX943_CCM_NUM_CLK_SRC + 99)
|
||||
#define IMX943_CLK_LPSPI8 (IMX943_CCM_NUM_CLK_SRC + 100)
|
||||
#define IMX943_CLK_LPTMR2 (IMX943_CCM_NUM_CLK_SRC + 101)
|
||||
#define IMX943_CLK_LPUART10 (IMX943_CCM_NUM_CLK_SRC + 102)
|
||||
#define IMX943_CLK_LPUART11 (IMX943_CCM_NUM_CLK_SRC + 103)
|
||||
#define IMX943_CLK_LPUART12 (IMX943_CCM_NUM_CLK_SRC + 104)
|
||||
#define IMX943_CLK_LPUART3 (IMX943_CCM_NUM_CLK_SRC + 105)
|
||||
#define IMX943_CLK_LPUART4 (IMX943_CCM_NUM_CLK_SRC + 106)
|
||||
#define IMX943_CLK_LPUART5 (IMX943_CCM_NUM_CLK_SRC + 107)
|
||||
#define IMX943_CLK_LPUART6 (IMX943_CCM_NUM_CLK_SRC + 108)
|
||||
#define IMX943_CLK_LPUART7 (IMX943_CCM_NUM_CLK_SRC + 109)
|
||||
#define IMX943_CLK_LPUART8 (IMX943_CCM_NUM_CLK_SRC + 110)
|
||||
#define IMX943_CLK_LPUART9 (IMX943_CCM_NUM_CLK_SRC + 111)
|
||||
#define IMX943_CLK_SAI2 (IMX943_CCM_NUM_CLK_SRC + 112)
|
||||
#define IMX943_CLK_SAI3 (IMX943_CCM_NUM_CLK_SRC + 113)
|
||||
#define IMX943_CLK_SAI4 (IMX943_CCM_NUM_CLK_SRC + 114)
|
||||
#define IMX943_CLK_SWOTRACE (IMX943_CCM_NUM_CLK_SRC + 115)
|
||||
#define IMX943_CLK_TPM4 (IMX943_CCM_NUM_CLK_SRC + 116)
|
||||
#define IMX943_CLK_TPM5 (IMX943_CCM_NUM_CLK_SRC + 117)
|
||||
#define IMX943_CLK_TPM6 (IMX943_CCM_NUM_CLK_SRC + 118)
|
||||
#define IMX943_CLK_USBPHYBURUNIN (IMX943_CCM_NUM_CLK_SRC + 119)
|
||||
#define IMX943_CLK_USDHC1 (IMX943_CCM_NUM_CLK_SRC + 120)
|
||||
#define IMX943_CLK_USDHC2 (IMX943_CCM_NUM_CLK_SRC + 121)
|
||||
#define IMX943_CLK_USDHC3 (IMX943_CCM_NUM_CLK_SRC + 122)
|
||||
#define IMX943_CLK_V2XPK (IMX943_CCM_NUM_CLK_SRC + 123)
|
||||
#define IMX943_CLK_WAKEUPAXI (IMX943_CCM_NUM_CLK_SRC + 124)
|
||||
#define IMX943_CLK_XSPISLVROOT (IMX943_CCM_NUM_CLK_SRC + 125)
|
||||
#define IMX943_CLK_XSPI1 (IMX943_CCM_NUM_CLK_SRC + 126)
|
||||
#define IMX943_CLK_XSPI2 (IMX943_CCM_NUM_CLK_SRC + 127)
|
||||
|
||||
#define IMX943_CLK_LDBPLL_VCO (IMX943_CCM_NUM_CLK_SRC + 29)
|
||||
#define IMX943_CLK_A55 (IMX943_CCM_NUM_CLK_SRC + 29)
|
||||
#define IMX943_CLK_A55MTRBUS (IMX943_CCM_NUM_CLK_SRC + 30)
|
||||
#define IMX943_CLK_A55PERIPH (IMX943_CCM_NUM_CLK_SRC + 31)
|
||||
#define IMX943_CLK_DRAMALT (IMX943_CCM_NUM_CLK_SRC + 32)
|
||||
#define IMX943_CLK_DRAMAPB (IMX943_CCM_NUM_CLK_SRC + 33)
|
||||
#define IMX943_CLK_DISPAPB (IMX943_CCM_NUM_CLK_SRC + 34)
|
||||
#define IMX943_CLK_DISPAXI (IMX943_CCM_NUM_CLK_SRC + 35)
|
||||
#define IMX943_CLK_DISPDP (IMX943_CCM_NUM_CLK_SRC + 36)
|
||||
#define IMX943_CLK_DISPOCRAM (IMX943_CCM_NUM_CLK_SRC + 37)
|
||||
#define IMX943_CLK_DISPUSB31 (IMX943_CCM_NUM_CLK_SRC + 38)
|
||||
#define IMX943_CLK_DISP1PIX (IMX943_CCM_NUM_CLK_SRC + 39)
|
||||
#define IMX943_CLK_DISP2PIX (IMX943_CCM_NUM_CLK_SRC + 40)
|
||||
#define IMX943_CLK_DISP3PIX (IMX943_CCM_NUM_CLK_SRC + 41)
|
||||
#define IMX943_CLK_GPUAPB (IMX943_CCM_NUM_CLK_SRC + 42)
|
||||
#define IMX943_CLK_GPU (IMX943_CCM_NUM_CLK_SRC + 43)
|
||||
#define IMX943_CLK_HSIOACSCAN480M (IMX943_CCM_NUM_CLK_SRC + 44)
|
||||
#define IMX943_CLK_HSIOACSCAN80M (IMX943_CCM_NUM_CLK_SRC + 45)
|
||||
#define IMX943_CLK_HSIO (IMX943_CCM_NUM_CLK_SRC + 46)
|
||||
#define IMX943_CLK_HSIOPCIEAUX (IMX943_CCM_NUM_CLK_SRC + 47)
|
||||
#define IMX943_CLK_HSIOPCIETEST160M (IMX943_CCM_NUM_CLK_SRC + 48)
|
||||
#define IMX943_CLK_HSIOPCIETEST400M (IMX943_CCM_NUM_CLK_SRC + 49)
|
||||
#define IMX943_CLK_HSIOPCIETEST500M (IMX943_CCM_NUM_CLK_SRC + 50)
|
||||
#define IMX943_CLK_HSIOUSBTEST50M (IMX943_CCM_NUM_CLK_SRC + 51)
|
||||
#define IMX943_CLK_HSIOUSBTEST60M (IMX943_CCM_NUM_CLK_SRC + 52)
|
||||
#define IMX943_CLK_BUSM7 (IMX943_CCM_NUM_CLK_SRC + 53)
|
||||
#define IMX943_CLK_M7 (IMX943_CCM_NUM_CLK_SRC + 54)
|
||||
#define IMX943_CLK_M7SYSTICK (IMX943_CCM_NUM_CLK_SRC + 55)
|
||||
#define IMX943_CLK_BUSNETCMIX (IMX943_CCM_NUM_CLK_SRC + 56)
|
||||
#define IMX943_CLK_ENET (IMX943_CCM_NUM_CLK_SRC + 57)
|
||||
#define IMX943_CLK_ENETPHYTEST200M (IMX943_CCM_NUM_CLK_SRC + 58)
|
||||
#define IMX943_CLK_ENETPHYTEST500M (IMX943_CCM_NUM_CLK_SRC + 59)
|
||||
#define IMX943_CLK_ENETPHYTEST667M (IMX943_CCM_NUM_CLK_SRC + 60)
|
||||
#define IMX943_CLK_ENETREF (IMX943_CCM_NUM_CLK_SRC + 61)
|
||||
#define IMX943_CLK_ENETTIMER1 (IMX943_CCM_NUM_CLK_SRC + 62)
|
||||
#define IMX943_CLK_MQS2 (IMX943_CCM_NUM_CLK_SRC + 63)
|
||||
#define IMX943_CLK_SAI2 (IMX943_CCM_NUM_CLK_SRC + 64)
|
||||
#define IMX943_CLK_NOCAPB (IMX943_CCM_NUM_CLK_SRC + 65)
|
||||
#define IMX943_CLK_NOC (IMX943_CCM_NUM_CLK_SRC + 66)
|
||||
#define IMX943_CLK_NPUAPB (IMX943_CCM_NUM_CLK_SRC + 67)
|
||||
#define IMX943_CLK_NPU (IMX943_CCM_NUM_CLK_SRC + 68)
|
||||
#define IMX943_CLK_CCMCKO1 (IMX943_CCM_NUM_CLK_SRC + 69)
|
||||
#define IMX943_CLK_CCMCKO2 (IMX943_CCM_NUM_CLK_SRC + 70)
|
||||
#define IMX943_CLK_CCMCKO3 (IMX943_CCM_NUM_CLK_SRC + 71)
|
||||
#define IMX943_CLK_CCMCKO4 (IMX943_CCM_NUM_CLK_SRC + 72)
|
||||
#define IMX943_CLK_VPUAPB (IMX943_CCM_NUM_CLK_SRC + 73)
|
||||
#define IMX943_CLK_VPU (IMX943_CCM_NUM_CLK_SRC + 74)
|
||||
#define IMX943_CLK_VPUDSP (IMX943_CCM_NUM_CLK_SRC + 75)
|
||||
#define IMX943_CLK_VPUJPEG (IMX943_CCM_NUM_CLK_SRC + 76)
|
||||
#define IMX943_CLK_AUDIOXCVR (IMX943_CCM_NUM_CLK_SRC + 77)
|
||||
#define IMX943_CLK_BUSWAKEUP (IMX943_CCM_NUM_CLK_SRC + 78)
|
||||
#define IMX943_CLK_CAN2 (IMX943_CCM_NUM_CLK_SRC + 79)
|
||||
#define IMX943_CLK_CAN3 (IMX943_CCM_NUM_CLK_SRC + 80)
|
||||
#define IMX943_CLK_CAN4 (IMX943_CCM_NUM_CLK_SRC + 81)
|
||||
#define IMX943_CLK_CAN5 (IMX943_CCM_NUM_CLK_SRC + 82)
|
||||
#define IMX943_CLK_FLEXIO1 (IMX943_CCM_NUM_CLK_SRC + 83)
|
||||
#define IMX943_CLK_FLEXIO2 (IMX943_CCM_NUM_CLK_SRC + 84)
|
||||
#define IMX943_CLK_FLEXSPI1 (IMX943_CCM_NUM_CLK_SRC + 85)
|
||||
#define IMX943_CLK_I3C2 (IMX943_CCM_NUM_CLK_SRC + 86)
|
||||
#define IMX943_CLK_I3C2SLOW (IMX943_CCM_NUM_CLK_SRC + 87)
|
||||
#define IMX943_CLK_LPI2C3 (IMX943_CCM_NUM_CLK_SRC + 88)
|
||||
#define IMX943_CLK_LPI2C4 (IMX943_CCM_NUM_CLK_SRC + 89)
|
||||
#define IMX943_CLK_LPI2C5 (IMX943_CCM_NUM_CLK_SRC + 90)
|
||||
#define IMX943_CLK_LPI2C6 (IMX943_CCM_NUM_CLK_SRC + 91)
|
||||
#define IMX943_CLK_LPI2C7 (IMX943_CCM_NUM_CLK_SRC + 92)
|
||||
#define IMX943_CLK_LPI2C8 (IMX943_CCM_NUM_CLK_SRC + 93)
|
||||
#define IMX943_CLK_LPSPI3 (IMX943_CCM_NUM_CLK_SRC + 94)
|
||||
#define IMX943_CLK_LPSPI4 (IMX943_CCM_NUM_CLK_SRC + 95)
|
||||
#define IMX943_CLK_LPSPI5 (IMX943_CCM_NUM_CLK_SRC + 96)
|
||||
#define IMX943_CLK_LPSPI6 (IMX943_CCM_NUM_CLK_SRC + 97)
|
||||
#define IMX943_CLK_LPSPI7 (IMX943_CCM_NUM_CLK_SRC + 98)
|
||||
#define IMX943_CLK_LPSPI8 (IMX943_CCM_NUM_CLK_SRC + 99)
|
||||
#define IMX943_CLK_LPTMR2 (IMX943_CCM_NUM_CLK_SRC + 100)
|
||||
#define IMX943_CLK_LPUART3 (IMX943_CCM_NUM_CLK_SRC + 101)
|
||||
#define IMX943_CLK_LPUART4 (IMX943_CCM_NUM_CLK_SRC + 102)
|
||||
#define IMX943_CLK_LPUART5 (IMX943_CCM_NUM_CLK_SRC + 103)
|
||||
#define IMX943_CLK_LPUART6 (IMX943_CCM_NUM_CLK_SRC + 104)
|
||||
#define IMX943_CLK_LPUART7 (IMX943_CCM_NUM_CLK_SRC + 105)
|
||||
#define IMX943_CLK_LPUART8 (IMX943_CCM_NUM_CLK_SRC + 106)
|
||||
#define IMX943_CLK_SAI3 (IMX943_CCM_NUM_CLK_SRC + 107)
|
||||
#define IMX943_CLK_SAI4 (IMX943_CCM_NUM_CLK_SRC + 108)
|
||||
#define IMX943_CLK_SAI5 (IMX943_CCM_NUM_CLK_SRC + 109)
|
||||
#define IMX943_CLK_SPDIF (IMX943_CCM_NUM_CLK_SRC + 110)
|
||||
#define IMX943_CLK_SWOTRACE (IMX943_CCM_NUM_CLK_SRC + 111)
|
||||
#define IMX943_CLK_TPM4 (IMX943_CCM_NUM_CLK_SRC + 112)
|
||||
#define IMX943_CLK_TPM5 (IMX943_CCM_NUM_CLK_SRC + 113)
|
||||
#define IMX943_CLK_TPM6 (IMX943_CCM_NUM_CLK_SRC + 114)
|
||||
#define IMX943_CLK_TSTMR2 (IMX943_CCM_NUM_CLK_SRC + 115)
|
||||
#define IMX943_CLK_USBPHYBURUNIN (IMX943_CCM_NUM_CLK_SRC + 116)
|
||||
#define IMX943_CLK_USDHC1 (IMX943_CCM_NUM_CLK_SRC + 117)
|
||||
#define IMX943_CLK_USDHC2 (IMX943_CCM_NUM_CLK_SRC + 118)
|
||||
#define IMX943_CLK_USDHC3 (IMX943_CCM_NUM_CLK_SRC + 119)
|
||||
#define IMX943_CLK_V2XPK (IMX943_CCM_NUM_CLK_SRC + 120)
|
||||
#define IMX943_CLK_WAKEUPAXI (IMX943_CCM_NUM_CLK_SRC + 121)
|
||||
#define IMX943_CLK_XSPISLVROOT (IMX943_CCM_NUM_CLK_SRC + 122)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX943_CLOCK_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue