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tests: fpu_sharing: Support FPU disable test for Cortex-A/R

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For testing, assume that the Cortex-A/R platforms are using a GIC
interrupt controller.  Use the last GIC SGI to trigger an interrupt for
the test.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
This commit is contained in:
Bradley Bolen 2022-04-07 10:56:21 -04:00 • committed by Stephanos Ioannidis
commit afef64e236
1 changed files with 17 additions and 0 deletions
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17
tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c
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@ -151,7 +151,11 @@ void test_k_float_disable_syscall(void)
#if defined(CONFIG_ARM) && defined(CONFIG_DYNAMIC_INTERRUPTS) #if defined(CONFIG_ARM) && defined(CONFIG_DYNAMIC_INTERRUPTS)
#include <arch/cpu.h> #include <arch/cpu.h>
#if defined(CONFIG_CPU_CORTEX_M)
#include <arch/arm/aarch32/cortex_m/cmsis.h> #include <arch/arm/aarch32/cortex_m/cmsis.h>
#else
#include <interrupt_util.h>
#endif
struct k_thread sup_fp_thread; struct k_thread sup_fp_thread;
K_THREAD_STACK_DEFINE(sup_fp_thread_stack, STACKSIZE); K_THREAD_STACK_DEFINE(sup_fp_thread_stack, STACKSIZE);
@ -180,6 +184,7 @@ static void sup_fp_thread_entry(void)
/* Determine an NVIC IRQ line that is not currently in use. */ /* Determine an NVIC IRQ line that is not currently in use. */
int i; int i;
#if defined(CONFIG_CPU_CORTEX_M)
for (i = CONFIG_NUM_IRQS - 1; i >= 0; i--) { for (i = CONFIG_NUM_IRQS - 1; i >= 0; i--) {
if (NVIC_GetEnableIRQ(i) == 0) { if (NVIC_GetEnableIRQ(i) == 0) {
/* /*
@ -191,6 +196,13 @@ static void sup_fp_thread_entry(void)
break; break;
} }
} }
#else
/*
* SGIs are always enabled by default, so choose the last one
* for testing.
*/
i = GIC_PPI_INT_BASE - 1;
#endif
zassert_true(i >= 0, zassert_true(i >= 0,
"No available IRQ line to use in the test\n"); "No available IRQ line to use in the test\n");
@ -203,9 +215,14 @@ static void sup_fp_thread_entry(void)
NULL, NULL,
0); 0);
#if defined(CONFIG_CPU_CORTEX_M)
NVIC_ClearPendingIRQ(i); NVIC_ClearPendingIRQ(i);
NVIC_EnableIRQ(i); NVIC_EnableIRQ(i);
NVIC_SetPendingIRQ(i); NVIC_SetPendingIRQ(i);
#else
arch_irq_enable(i);
trigger_irq(i);
#endif
/* /*
* Instruction barriers to make sure the NVIC IRQ is * Instruction barriers to make sure the NVIC IRQ is