From afef64e2369548a209387e1e35efa0660e7147e8 Mon Sep 17 00:00:00 2001 From: Bradley Bolen Date: Thu, 7 Apr 2022 10:56:21 -0400 Subject: [PATCH] tests: fpu_sharing: Support FPU disable test for Cortex-A/R For testing, assume that the Cortex-A/R platforms are using a GIC interrupt controller. Use the last GIC SGI to trigger an interrupt for the test. Signed-off-by: Bradley Bolen --- .../float_disable/src/k_float_disable.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c b/tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c index 56a3460ab09..b9dcc103a4e 100644 --- a/tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c +++ b/tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c @@ -151,7 +151,11 @@ void test_k_float_disable_syscall(void) #if defined(CONFIG_ARM) && defined(CONFIG_DYNAMIC_INTERRUPTS) #include +#if defined(CONFIG_CPU_CORTEX_M) #include +#else +#include +#endif struct k_thread sup_fp_thread; K_THREAD_STACK_DEFINE(sup_fp_thread_stack, STACKSIZE); @@ -180,6 +184,7 @@ static void sup_fp_thread_entry(void) /* Determine an NVIC IRQ line that is not currently in use. */ int i; +#if defined(CONFIG_CPU_CORTEX_M) for (i = CONFIG_NUM_IRQS - 1; i >= 0; i--) { if (NVIC_GetEnableIRQ(i) == 0) { /* @@ -191,6 +196,13 @@ static void sup_fp_thread_entry(void) break; } } +#else + /* + * SGIs are always enabled by default, so choose the last one + * for testing. + */ + i = GIC_PPI_INT_BASE - 1; +#endif zassert_true(i >= 0, "No available IRQ line to use in the test\n"); @@ -203,9 +215,14 @@ static void sup_fp_thread_entry(void) NULL, 0); +#if defined(CONFIG_CPU_CORTEX_M) NVIC_ClearPendingIRQ(i); NVIC_EnableIRQ(i); NVIC_SetPendingIRQ(i); +#else + arch_irq_enable(i); + trigger_irq(i); +#endif /* * Instruction barriers to make sure the NVIC IRQ is