From af3d5331a19e97d952e1b0c94eecaa5f31ea4bb2 Mon Sep 17 00:00:00 2001
From: Anas Nashif <anas.nashif@intel.com>
Date: Thu, 14 Jul 2022 10:59:07 -0400
Subject: [PATCH] intel-adsp: migrate cavs-mem.h to adsp_memory.h

Move header and make it soc specific.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
---
 drivers/ipm/ipm_cavs_host.c                   |  2 +-
 drivers/mm/mm_drv_intel_adsp_mtl_tlb.c        |  2 +-
 drivers/mm/mm_drv_intel_adsp_tlb.c            |  2 +-
 soc/xtensa/intel_adsp/ace_v1x/ace-link.ld     |  2 +-
 .../intel_adsp/ace_v1x/include/adsp_memory.h  | 31 +++++++++++++++++++
 .../intel_adsp/ace_v1x/multiprocessing.c      |  2 +-
 soc/xtensa/intel_adsp/ace_v1x/soc.c           |  2 +-
 .../intel_adsp/cavs_v15/include/adsp_memory.h | 31 +++++++++++++++++++
 .../intel_adsp/cavs_v18/include/adsp_memory.h | 31 +++++++++++++++++++
 .../intel_adsp/cavs_v20/include/adsp_memory.h | 31 +++++++++++++++++++
 .../intel_adsp/cavs_v25/include/adsp_memory.h | 31 +++++++++++++++++++
 soc/xtensa/intel_adsp/common/boot.c           |  2 +-
 .../intel_adsp/common/include/cavs-link.ld    |  2 +-
 .../intel_adsp/common/include/cavs-mem.h      | 30 +-----------------
 .../common/include/intel_adsp_hda.h           |  2 +-
 .../intel_adsp/common/multiprocessing.c       |  2 +-
 .../intel_adsp/common/multiprocessing_cavs.c  |  2 +-
 soc/xtensa/intel_adsp/common/rimage_modules.c |  2 +-
 soc/xtensa/intel_adsp/common/sram.c           |  2 +-
 soc/xtensa/intel_adsp/common/trace_out.c      |  2 +-
 tests/boards/intel_adsp/mm/src/main.c         |  2 +-
 21 files changed, 171 insertions(+), 44 deletions(-)

diff --git a/drivers/ipm/ipm_cavs_host.c b/drivers/ipm/ipm_cavs_host.c
index 9d6a95d129e..ac135e2f3ff 100644
--- a/drivers/ipm/ipm_cavs_host.c
+++ b/drivers/ipm/ipm_cavs_host.c
@@ -3,7 +3,7 @@
  */
 #include <zephyr/kernel.h>
 #include <zephyr/drivers/ipm.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 #include <adsp_shim.h>
 #include <cavs_ipc.h>
 
diff --git a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c
index 908e9042782..e473d5f5289 100644
--- a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c
+++ b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c
@@ -33,7 +33,7 @@
 #include <zephyr/sys/mem_blocks.h>
 
 #include <soc.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 
 #include "mm_drv_common.h"
 
diff --git a/drivers/mm/mm_drv_intel_adsp_tlb.c b/drivers/mm/mm_drv_intel_adsp_tlb.c
index cd10c58c45a..3ec3b54228e 100644
--- a/drivers/mm/mm_drv_intel_adsp_tlb.c
+++ b/drivers/mm/mm_drv_intel_adsp_tlb.c
@@ -31,7 +31,7 @@
 #include <zephyr/sys/util.h>
 
 #include <soc.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 
 #include <zephyr/drivers/mm/system_mm.h>
 #include "mm_drv_common.h"
diff --git a/soc/xtensa/intel_adsp/ace_v1x/ace-link.ld b/soc/xtensa/intel_adsp/ace_v1x/ace-link.ld
index e49a382b29c..04a08accebe 100644
--- a/soc/xtensa/intel_adsp/ace_v1x/ace-link.ld
+++ b/soc/xtensa/intel_adsp/ace_v1x/ace-link.ld
@@ -17,7 +17,7 @@ OUTPUT_ARCH(xtensa)
 #include <xtensa/config/core-isa.h>
 #include <zephyr/linker/sections.h>
 #include <cavs-vectors.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 
 #include <zephyr/linker/linker-defs.h>
 #include <zephyr/linker/linker-tool.h>
diff --git a/soc/xtensa/intel_adsp/ace_v1x/include/adsp_memory.h b/soc/xtensa/intel_adsp/ace_v1x/include/adsp_memory.h
index 798b9bd27c8..acd9bdd92a6 100644
--- a/soc/xtensa/intel_adsp/ace_v1x/include/adsp_memory.h
+++ b/soc/xtensa/intel_adsp/ace_v1x/include/adsp_memory.h
@@ -6,6 +6,37 @@
 #ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
 #define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
 
+
+#include <zephyr/devicetree.h>
+#include <cavs-vectors.h>
+
+#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
+#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
+
+#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
+#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
+
+#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
+
+/* Linker-usable RAM region */
+#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
+#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
+
+/* Host shared memory windows */
+#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
+#define HP_SRAM_WIN0_SIZE 0x2000
+#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
+#define HP_SRAM_WIN3_SIZE 0x2000
+
+/* The rimage tool produces two blob addresses we need to find: one is
+ * our bootloader code block which starts at its entry point, the
+ * other is the "manifest" containing the HP-SRAM data to unpack,
+ * which appears 24k earlier in the DMA'd file, and thus in IMR
+ * memory.  There's no ability to change this offset, it's a magic
+ * number from rimage we simply need to honor.
+ */
+#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
+
 #define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038
 
 #endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
diff --git a/soc/xtensa/intel_adsp/ace_v1x/multiprocessing.c b/soc/xtensa/intel_adsp/ace_v1x/multiprocessing.c
index 58a8e5b5a46..455a847658e 100644
--- a/soc/xtensa/intel_adsp/ace_v1x/multiprocessing.c
+++ b/soc/xtensa/intel_adsp/ace_v1x/multiprocessing.c
@@ -10,7 +10,7 @@
 #include <soc.h>
 #include <ace_v1x-regs.h>
 #include <ace-ipc-regs.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 
 #define CORE_POWER_CHECK_NUM 32
 #define CORE_POWER_CHECK_DELAY 256
diff --git a/soc/xtensa/intel_adsp/ace_v1x/soc.c b/soc/xtensa/intel_adsp/ace_v1x/soc.c
index 2ca41950750..987e890a95a 100644
--- a/soc/xtensa/intel_adsp/ace_v1x/soc.c
+++ b/soc/xtensa/intel_adsp/ace_v1x/soc.c
@@ -8,7 +8,7 @@
 #include <zephyr/irq_nextlevel.h>
 
 #include <ace_v1x-regs.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 #include <adsp_shim.h>
 #include <cpu_init.h>
 #include <soc.h>
diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/adsp_memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/adsp_memory.h
index 40592b72d91..52148075b9f 100644
--- a/soc/xtensa/intel_adsp/cavs_v15/include/adsp_memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v15/include/adsp_memory.h
@@ -6,6 +6,37 @@
 #ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
 #define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
 
+
+#include <zephyr/devicetree.h>
+#include <cavs-vectors.h>
+
+#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
+#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
+
+#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
+#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
+
+#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
+
+/* Linker-usable RAM region */
+#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
+#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
+
+/* Host shared memory windows */
+#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
+#define HP_SRAM_WIN0_SIZE 0x2000
+#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
+#define HP_SRAM_WIN3_SIZE 0x2000
+
+/* The rimage tool produces two blob addresses we need to find: one is
+ * our bootloader code block which starts at its entry point, the
+ * other is the "manifest" containing the HP-SRAM data to unpack,
+ * which appears 24k earlier in the DMA'd file, and thus in IMR
+ * memory.  There's no ability to change this offset, it's a magic
+ * number from rimage we simply need to honor.
+ */
+#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
+
 #define ADSP_L1_CACHE_PREFCTL_VALUE 0
 
 #endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/adsp_memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/adsp_memory.h
index 40592b72d91..52148075b9f 100644
--- a/soc/xtensa/intel_adsp/cavs_v18/include/adsp_memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v18/include/adsp_memory.h
@@ -6,6 +6,37 @@
 #ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
 #define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
 
+
+#include <zephyr/devicetree.h>
+#include <cavs-vectors.h>
+
+#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
+#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
+
+#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
+#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
+
+#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
+
+/* Linker-usable RAM region */
+#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
+#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
+
+/* Host shared memory windows */
+#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
+#define HP_SRAM_WIN0_SIZE 0x2000
+#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
+#define HP_SRAM_WIN3_SIZE 0x2000
+
+/* The rimage tool produces two blob addresses we need to find: one is
+ * our bootloader code block which starts at its entry point, the
+ * other is the "manifest" containing the HP-SRAM data to unpack,
+ * which appears 24k earlier in the DMA'd file, and thus in IMR
+ * memory.  There's no ability to change this offset, it's a magic
+ * number from rimage we simply need to honor.
+ */
+#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
+
 #define ADSP_L1_CACHE_PREFCTL_VALUE 0
 
 #endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/adsp_memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/adsp_memory.h
index 40592b72d91..52148075b9f 100644
--- a/soc/xtensa/intel_adsp/cavs_v20/include/adsp_memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v20/include/adsp_memory.h
@@ -6,6 +6,37 @@
 #ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
 #define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
 
+
+#include <zephyr/devicetree.h>
+#include <cavs-vectors.h>
+
+#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
+#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
+
+#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
+#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
+
+#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
+
+/* Linker-usable RAM region */
+#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
+#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
+
+/* Host shared memory windows */
+#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
+#define HP_SRAM_WIN0_SIZE 0x2000
+#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
+#define HP_SRAM_WIN3_SIZE 0x2000
+
+/* The rimage tool produces two blob addresses we need to find: one is
+ * our bootloader code block which starts at its entry point, the
+ * other is the "manifest" containing the HP-SRAM data to unpack,
+ * which appears 24k earlier in the DMA'd file, and thus in IMR
+ * memory.  There's no ability to change this offset, it's a magic
+ * number from rimage we simply need to honor.
+ */
+#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
+
 #define ADSP_L1_CACHE_PREFCTL_VALUE 0
 
 #endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/adsp_memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/adsp_memory.h
index 798b9bd27c8..acd9bdd92a6 100644
--- a/soc/xtensa/intel_adsp/cavs_v25/include/adsp_memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v25/include/adsp_memory.h
@@ -6,6 +6,37 @@
 #ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
 #define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
 
+
+#include <zephyr/devicetree.h>
+#include <cavs-vectors.h>
+
+#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
+#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
+
+#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
+#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
+
+#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
+
+/* Linker-usable RAM region */
+#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
+#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
+
+/* Host shared memory windows */
+#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
+#define HP_SRAM_WIN0_SIZE 0x2000
+#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
+#define HP_SRAM_WIN3_SIZE 0x2000
+
+/* The rimage tool produces two blob addresses we need to find: one is
+ * our bootloader code block which starts at its entry point, the
+ * other is the "manifest" containing the HP-SRAM data to unpack,
+ * which appears 24k earlier in the DMA'd file, and thus in IMR
+ * memory.  There's no ability to change this offset, it's a magic
+ * number from rimage we simply need to honor.
+ */
+#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
+
 #define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038
 
 #endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
diff --git a/soc/xtensa/intel_adsp/common/boot.c b/soc/xtensa/intel_adsp/common/boot.c
index df3e4d5b303..2a6625af6ba 100644
--- a/soc/xtensa/intel_adsp/common/boot.c
+++ b/soc/xtensa/intel_adsp/common/boot.c
@@ -9,7 +9,7 @@
 #include <soc.h>
 #include <zephyr/arch/xtensa/cache.h>
 #include <adsp_shim.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 #include <cpu_init.h>
 #include "manifest.h"
 
diff --git a/soc/xtensa/intel_adsp/common/include/cavs-link.ld b/soc/xtensa/intel_adsp/common/include/cavs-link.ld
index a26647153af..b2e999fb3a7 100644
--- a/soc/xtensa/intel_adsp/common/include/cavs-link.ld
+++ b/soc/xtensa/intel_adsp/common/include/cavs-link.ld
@@ -17,7 +17,7 @@ OUTPUT_ARCH(xtensa)
 #include <xtensa/config/core-isa.h>
 #include <zephyr/linker/sections.h>
 #include <cavs-vectors.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 
 #include <zephyr/linker/linker-defs.h>
 #include <zephyr/linker/linker-tool.h>
diff --git a/soc/xtensa/intel_adsp/common/include/cavs-mem.h b/soc/xtensa/intel_adsp/common/include/cavs-mem.h
index 88299a60081..6ef37d066c0 100644
--- a/soc/xtensa/intel_adsp/common/include/cavs-mem.h
+++ b/soc/xtensa/intel_adsp/common/include/cavs-mem.h
@@ -4,34 +4,6 @@
 #ifndef _ZEPHYR_SOC_INTEL_ADSP_MEM
 #define _ZEPHYR_SOC_INTEL_ADSP_MEM
 
-#include <zephyr/devicetree.h>
-#include <cavs-vectors.h>
-
-#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
-#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
-
-#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
-#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
-
-#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
-
-/* Linker-usable RAM region */
-#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
-#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
-
-/* Host shared memory windows */
-#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
-#define HP_SRAM_WIN0_SIZE 0x2000
-#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
-#define HP_SRAM_WIN3_SIZE 0x2000
-
-/* The rimage tool produces two blob addresses we need to find: one is
- * our bootloader code block which starts at its entry point, the
- * other is the "manifest" containing the HP-SRAM data to unpack,
- * which appears 24k earlier in the DMA'd file, and thus in IMR
- * memory.  There's no ability to change this offset, it's a magic
- * number from rimage we simply need to honor.
- */
-#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
+#include <adsp_memory.h>
 
 #endif /* _ZEPHYR_SOC_INTEL_ADSP_MEM */
diff --git a/soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h b/soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h
index 472b128d007..6192b181bad 100644
--- a/soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h
+++ b/soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h
@@ -9,7 +9,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <adsp_shim.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 
 /**
  * @brief HDA stream functionality for Intel ADSP
diff --git a/soc/xtensa/intel_adsp/common/multiprocessing.c b/soc/xtensa/intel_adsp/common/multiprocessing.c
index 0cd2bf5ab37..c1f0d4a6c6d 100644
--- a/soc/xtensa/intel_adsp/common/multiprocessing.c
+++ b/soc/xtensa/intel_adsp/common/multiprocessing.c
@@ -22,7 +22,7 @@ LOG_MODULE_REGISTER(soc_mp, CONFIG_SOC_LOG_LEVEL);
 #include <soc.h>
 #include <zephyr/arch/xtensa/cache.h>
 #include <adsp_shim.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 #include <cpu_init.h>
 
 struct cpustart_rec {
diff --git a/soc/xtensa/intel_adsp/common/multiprocessing_cavs.c b/soc/xtensa/intel_adsp/common/multiprocessing_cavs.c
index eb802e51f4e..0d7ce45e1c6 100644
--- a/soc/xtensa/intel_adsp/common/multiprocessing_cavs.c
+++ b/soc/xtensa/intel_adsp/common/multiprocessing_cavs.c
@@ -3,7 +3,7 @@
  */
 #include <zephyr/zephyr.h>
 #include <cavs-idc.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 #include <adsp_shim.h>
 
 /* IDC power up message to the ROM firmware.  This isn't documented
diff --git a/soc/xtensa/intel_adsp/common/rimage_modules.c b/soc/xtensa/intel_adsp/common/rimage_modules.c
index e3583b3fb51..fd4bca1137c 100644
--- a/soc/xtensa/intel_adsp/common/rimage_modules.c
+++ b/soc/xtensa/intel_adsp/common/rimage_modules.c
@@ -2,7 +2,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <manifest.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 #include <zephyr/toolchain.h>
 
 /* These two modules defined here aren't runtime data used by Zephyr or
diff --git a/soc/xtensa/intel_adsp/common/sram.c b/soc/xtensa/intel_adsp/common/sram.c
index 26b7c46e578..08d898fec2a 100644
--- a/soc/xtensa/intel_adsp/common/sram.c
+++ b/soc/xtensa/intel_adsp/common/sram.c
@@ -9,7 +9,7 @@
 #include <soc.h>
 #include <zephyr/arch/xtensa/cache.h>
 #include <adsp_shim.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 #include <cpu_init.h>
 #include "manifest.h"
 
diff --git a/soc/xtensa/intel_adsp/common/trace_out.c b/soc/xtensa/intel_adsp/common/trace_out.c
index fff021786dd..68978ce8a17 100644
--- a/soc/xtensa/intel_adsp/common/trace_out.c
+++ b/soc/xtensa/intel_adsp/common/trace_out.c
@@ -3,7 +3,7 @@
  */
 #include <zephyr/zephyr.h>
 #include <soc.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 #include <zephyr/sys/winstream.h>
 
 struct k_spinlock trace_lock;
diff --git a/tests/boards/intel_adsp/mm/src/main.c b/tests/boards/intel_adsp/mm/src/main.c
index bc2078e623f..4edf89b8f8c 100644
--- a/tests/boards/intel_adsp/mm/src/main.c
+++ b/tests/boards/intel_adsp/mm/src/main.c
@@ -14,7 +14,7 @@
 #include <zephyr/drivers/mm/system_mm.h>
 
 #include <soc.h>
-#include <cavs-mem.h>
+#include <adsp_memory.h>
 
 #define N_PAGES 3
 #define PAGE_SZ CONFIG_MM_DRV_PAGE_SIZE