michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: espressif: adjust memory organization on linker

Browse source 
Adjust the memory organization to avoid overlapping
critical regions from bootloaders (MCUboot and IDF)

Signed-off-by: Almir Okato <almir.okato@espressif.com>
This commit is contained in:
Almir Okato 2023-08-13 11:17:54 -03:00 • committed by Carles Cufí
commit af3b04238e
4 changed files with 9 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

4
soc/riscv/espressif_esp32/esp32c3/default.ld
View file

@ -26,7 +26,9 @@
#define SRAM_DRAM_START 0x3FC7C000 #define SRAM_DRAM_START 0x3FC7C000
#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */ #define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */
#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) #define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ /* SRAM_DRAM_END is equivalent 2nd stage bootloader iram_loader_seg
start address (that should not be overlapped) */
#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET
#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE) #define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE)
#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE) #define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE)
#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG #define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG

3
soc/xtensa/espressif_esp32/esp32/default.ld
View file

@ -39,13 +39,12 @@
#define IROM_SEG_ORG 0x400D0020 #define IROM_SEG_ORG 0x400D0020
#define IROM_SEG_LEN FLASH_SIZE-0x20 #define IROM_SEG_LEN FLASH_SIZE-0x20
#define IROM_SEG_ALIGN 0x4 #define IROM_SEG_ALIGN 0x4
#define IRAM_SEG_LEN 0x20000
#else #else
#define IROM_SEG_ORG 0x400D0000 #define IROM_SEG_ORG 0x400D0000
#define IROM_SEG_LEN FLASH_SIZE #define IROM_SEG_LEN FLASH_SIZE
#define IROM_SEG_ALIGN 0x10000 #define IROM_SEG_ALIGN 0x10000
#define IRAM_SEG_LEN 0x13000
#endif #endif
#define IRAM_SEG_LEN 0x20000
MEMORY MEMORY
{ {

4
soc/xtensa/espressif_esp32/esp32s2/default.ld
View file

@ -18,7 +18,9 @@
#define RAM_IRAM_START 0x40020000 #define RAM_IRAM_START 0x40020000
#define RAM_DRAM_START 0x3ffb0000 #define RAM_DRAM_START 0x3ffb0000
#define DATA_RAM_END 0x40000000 /* DATA_RAM_END is equivalent 2nd stage bootloader iram_loader_seg
start address (that should not be overlapped) */
#define DATA_RAM_END 0x3FFE0000
#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \ #define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
+ CONFIG_ESP32S2_DATA_CACHE_SIZE) + CONFIG_ESP32S2_DATA_CACHE_SIZE)

2
soc/xtensa/espressif_esp32/esp32s3/default.ld
View file

@ -17,6 +17,8 @@
#define SRAM_IRAM_START 0x40370000 #define SRAM_IRAM_START 0x40370000
#define SRAM_DIRAM_I_START 0x40378000 #define SRAM_DIRAM_I_START 0x40378000
/* SRAM_IRAM_END is equivalent 2nd stage bootloader iram_loader_seg
start address (that should not be overlapped) */
#define SRAM_IRAM_END 0x403BA000 #define SRAM_IRAM_END 0x403BA000
#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START) #define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)