From af3b04238e342472f594100553a9a652be1ef331 Mon Sep 17 00:00:00 2001 From: Almir Okato Date: Sun, 13 Aug 2023 11:17:54 -0300 Subject: [PATCH] soc: espressif: adjust memory organization on linker Adjust the memory organization to avoid overlapping critical regions from bootloaders (MCUboot and IDF) Signed-off-by: Almir Okato --- soc/riscv/espressif_esp32/esp32c3/default.ld | 4 +++- soc/xtensa/espressif_esp32/esp32/default.ld | 3 +-- soc/xtensa/espressif_esp32/esp32s2/default.ld | 4 +++- soc/xtensa/espressif_esp32/esp32s3/default.ld | 2 ++ 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/soc/riscv/espressif_esp32/esp32c3/default.ld b/soc/riscv/espressif_esp32/esp32c3/default.ld index 13d08d39bee..01aeb903af2 100644 --- a/soc/riscv/espressif_esp32/esp32c3/default.ld +++ b/soc/riscv/espressif_esp32/esp32c3/default.ld @@ -26,7 +26,9 @@ #define SRAM_DRAM_START 0x3FC7C000 #define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */ #define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) -#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ +/* SRAM_DRAM_END is equivalent 2nd stage bootloader iram_loader_seg + start address (that should not be overlapped) */ +#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET #define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE) #define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE) #define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG diff --git a/soc/xtensa/espressif_esp32/esp32/default.ld b/soc/xtensa/espressif_esp32/esp32/default.ld index 83e2d0300d7..b04399a24ac 100644 --- a/soc/xtensa/espressif_esp32/esp32/default.ld +++ b/soc/xtensa/espressif_esp32/esp32/default.ld @@ -39,13 +39,12 @@ #define IROM_SEG_ORG 0x400D0020 #define IROM_SEG_LEN FLASH_SIZE-0x20 #define IROM_SEG_ALIGN 0x4 -#define IRAM_SEG_LEN 0x20000 #else #define IROM_SEG_ORG 0x400D0000 #define IROM_SEG_LEN FLASH_SIZE #define IROM_SEG_ALIGN 0x10000 -#define IRAM_SEG_LEN 0x13000 #endif +#define IRAM_SEG_LEN 0x20000 MEMORY { diff --git a/soc/xtensa/espressif_esp32/esp32s2/default.ld b/soc/xtensa/espressif_esp32/esp32s2/default.ld index bac485535e1..c6681215e5d 100644 --- a/soc/xtensa/espressif_esp32/esp32s2/default.ld +++ b/soc/xtensa/espressif_esp32/esp32s2/default.ld @@ -18,7 +18,9 @@ #define RAM_IRAM_START 0x40020000 #define RAM_DRAM_START 0x3ffb0000 -#define DATA_RAM_END 0x40000000 +/* DATA_RAM_END is equivalent 2nd stage bootloader iram_loader_seg + start address (that should not be overlapped) */ +#define DATA_RAM_END 0x3FFE0000 #define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \ + CONFIG_ESP32S2_DATA_CACHE_SIZE) diff --git a/soc/xtensa/espressif_esp32/esp32s3/default.ld b/soc/xtensa/espressif_esp32/esp32s3/default.ld index 02014a2718d..b3cbd62c89b 100644 --- a/soc/xtensa/espressif_esp32/esp32s3/default.ld +++ b/soc/xtensa/espressif_esp32/esp32s3/default.ld @@ -17,6 +17,8 @@ #define SRAM_IRAM_START 0x40370000 #define SRAM_DIRAM_I_START 0x40378000 +/* SRAM_IRAM_END is equivalent 2nd stage bootloader iram_loader_seg + start address (that should not be overlapped) */ #define SRAM_IRAM_END 0x403BA000 #define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)