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soc: espressif: adjust memory organization on linker

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Adjust the memory organization to avoid overlapping
critical regions from bootloaders (MCUboot and IDF)

Signed-off-by: Almir Okato <almir.okato@espressif.com>
This commit is contained in:
Almir Okato 2023-08-13 11:17:54 -03:00 • committed by Carles Cufí
commit af3b04238e
4 changed files with 9 additions and 4 deletions
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4
soc/riscv/espressif_esp32/esp32c3/default.ld
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@ -26,7 +26,9 @@
#define SRAM_DRAM_START 0x3FC7C000
#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */
#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
/* SRAM_DRAM_END is equivalent 2nd stage bootloader iram_loader_seg
start address (that should not be overlapped) */
#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET
#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE)
#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE)
#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG