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soc: imx8mm/n: fix pinctrl field shifting value

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The lowest bit in DSE and FSEL field of pinctl register is not used
in the register and dts binding definitions also don't conver this bit,
so shift one more bit to align with actual register definitions.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
This commit is contained in:
Jiafei Pan 2025-02-25 16:39:15 +08:00 • committed by Fabio Baltieri
commit af2f497ad0
2 changed files with 12 additions and 4 deletions
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11
soc/nxp/imx/imx8m/a53/pinctrl_soc.h
View file

@ -19,11 +19,18 @@ extern "C" {
#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT #define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT
#define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT #define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT
#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT #define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT
#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */ #define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1) #define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
#if defined(CONFIG_SOC_MIMX8MM6_A53) || defined(CONFIG_SOC_MIMX8MN6_A53)
/* fixed for DSE and FSEL for as there is one bit not used in these field */
#define MCUX_IMX_SLEW_RATE_SHIFT (IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT + 1)
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT (IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT + 1)
#else
#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
#endif
#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \ #define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \
((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \ ((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \ (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \

5
soc/nxp/imx/imx8m/m4_mini/pinctrl_soc.h
View file

@ -19,8 +19,9 @@ extern "C" {
#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT #define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT
#define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT #define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT
#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT #define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT
#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT /* fixed for DSE and FSEL for as there is one bit not used in these field */
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT #define MCUX_IMX_SLEW_RATE_SHIFT (IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT + 1)
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT (IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT + 1)
#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */ #define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1) #define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)