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soc: renesas: ra: ra4m1: Adapts the Option Setting Memory to FSP.

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Since the Option Setting Memory area is set in FSP, the Kconfig value
switches between using the FSP implementation or the existing
Option Setting Memory implementation.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit is contained in:
TOKITA Hiroshi 2024-08-21 23:12:51 +09:00 • committed by Fabio Baltieri
commit af2021ea4c
3 changed files with 25 additions and 54 deletions
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5
soc/renesas/ra/ra4m1/CMakeLists.txt
View file

@ -5,11 +5,6 @@ zephyr_include_directories(.)
zephyr_library_sources(soc.c)
zephyr_linker_sources_ifdef(CONFIG_SOC_OPTION_SETTING_MEMORY
ROM_START
${CMAKE_CURRENT_SOURCE_DIR}/opt_set_mem.ld
)
zephyr_linker_sources(SECTIONS sections.ld)
zephyr_linker_sources(DATA_SECTIONS data_sections.ld)
zephyr_linker_sources(RAM_SECTIONS ram_sections.ld)

11
soc/renesas/ra/ra4m1/opt_set_mem.ld
View file

@ -1,11 +0,0 @@
/*
* Copyright (c) 2024 Ian Morris
*
* SPDX-License-Identifier: Apache-2.0
*
*/
. = 0x400;
FILL(0xFF)
KEEP(*(.opt_set_mem*))
. = 0x500;

63
soc/renesas/ra/ra4m1/soc.c
View file

@ -23,7 +23,7 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
#include "bsp_cfg.h"
#include <bsp_api.h>
#define HOCO_FREQ DT_PROP(DT_PATH(clocks, hoco), clock_frequency)
#define HOCO_FREQ DT_PROP(DT_PATH(clocks, clock_hoco), clock_frequency)
#if HOCO_FREQ == MHZ(24)
#define OFS1_HOCO_FREQ 0
@ -93,43 +93,31 @@ struct opt_set_mem {
};
#ifdef CONFIG_SOC_OPTION_SETTING_MEMORY
const struct opt_set_mem ops __attribute__((section(".opt_set_mem"))) = {
const struct opt_set_mem ops __attribute__((section(".rom_registers"))) = {
.ofs0 = {
/*
* Initial settings for watchdog timers. Set all fields to 1,
* disabling watchdog functionality as config options have not
* yet been implemented.
*/
.RSVD1 = 0x1,
.IWDTSTRT = 0x1, /* Disable independent watchdog timer */
.IWDTTOPS = 0x3,
.IWDTCKS = 0xf,
.IWDTRPES = 0x3,
.IWDTRPSS = 0x3,
.IWDTRSTIRQS = 0x1,
.RSVD2 = 0x1,
.IWDTSTPCTL = 0x1,
.RSVD3 = 0x3,
.WDTSTRT = 0x1, /* Stop watchdog timer following reset */
.WDTTOPS = 0x3,
.WDTCKS = 0xf,
.WDTRPES = 0x3,
.WDTRPSS = 0x3,
.WDTRSTIRQS = 0x1,
.RSVD4 = 0x1,
.WDTSTPCTL = 0x1,
.RSVD5 = 0x1,
},
/*
* Initial settings for watchdog timers. Set all fields to 1,
* disabling watchdog functionality as config options have not
* yet been implemented.
*/
.RSVD1 = 0x1, .IWDTSTRT = 0x1, /* Disable independent watchdog timer
*/
.IWDTTOPS = 0x3, .IWDTCKS = 0xf, .IWDTRPES = 0x3, .IWDTRPSS = 0x3,
.IWDTRSTIRQS = 0x1, .RSVD2 = 0x1, .IWDTSTPCTL = 0x1, .RSVD3 = 0x3,
.WDTSTRT = 0x1, /* Stop watchdog timer following reset */
.WDTTOPS = 0x3, .WDTCKS = 0xf, .WDTRPES = 0x3, .WDTRPSS = 0x3,
.WDTRSTIRQS = 0x1, .RSVD4 = 0x1, .WDTSTPCTL = 0x1, .RSVD5 = 0x1,
},
.ofs1 = {
.RSVD1 = 0x3,
.LVDAS = 0x1, /* Disable voltage monitor 0 following reset */
.VDSEL1 = 0x3,
.RSVD2 = 0x3,
.HOCOEN = !DT_NODE_HAS_STATUS_OKAY(DT_PATH(clocks, hoco)),
.RSVD3 = 0x7,
.HOCOFRQ1 = OFS1_HOCO_FREQ,
.RSVD4 = 0x1ffff,
},
.RSVD1 = 0x3,
.LVDAS = 0x1, /* Disable voltage monitor 0 following reset */
.VDSEL1 = 0x3,
.RSVD2 = 0x3,
.HOCOEN = !DT_NODE_HAS_STATUS(DT_PATH(clocks, clock_hoco), okay),
.RSVD3 = 0x7,
.HOCOFRQ1 = OFS1_HOCO_FREQ,
.RSVD4 = 0x1ffff,
},
.mpu = {
/*
* Initial settings for MPU. Set all areas to maximum values
@ -149,8 +137,7 @@ const struct opt_set_mem ops __attribute__((section(".opt_set_mem"))) = {
.SECMPUS3 = 0x40dffffc,
.SECMPUE3 = 0x40dfffff,
.SECMPUAC = 0xffffffff,
}
};
}};
#endif
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;