drivers: spi: spi_sam0: rework devicetree support
Rework the devicetree to utilize new DT_INST macros and extract per instance data for clocks and dma from devicetree. We update the atmel,sam0-spi binding for dma to replace the rxdma and txdma properties with proper 'dmas' property. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Kumar Gala
parent
b8ade7856d
commit
aa63b07019
2 changed files with 52 additions and 116 deletions
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@ -3,6 +3,7 @@
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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#define DT_DRV_COMPAT atmel_sam0_spi
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <logging/log.h>
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#include <logging/log.h>
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@ -723,122 +724,50 @@ static const struct spi_driver_api spi_sam0_driver_api = {
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};
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};
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#if CONFIG_SPI_ASYNC
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#if CONFIG_SPI_ASYNC
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_0_TXDMA
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#define SPI_SAM0_DMA_CHANNELS(n) \
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#define DT_ATMEL_SAM0_SPI_SERCOM_0_TXDMA 0xFF
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.tx_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, tx), \
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#endif
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.tx_dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, tx), \
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_0_RXDMA
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.rx_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, rx), \
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#define DT_ATMEL_SAM0_SPI_SERCOM_0_RXDMA 0xFF
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.rx_dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, rx),
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#endif
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_1_TXDMA
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#define DT_ATMEL_SAM0_SPI_SERCOM_1_TXDMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_1_RXDMA
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#define DT_ATMEL_SAM0_SPI_SERCOM_1_RXDMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_2_TXDMA
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#define DT_ATMEL_SAM0_SPI_SERCOM_2_TXDMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_2_RXDMA
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#define DT_ATMEL_SAM0_SPI_SERCOM_2_RXDMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_3_TXDMA
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#define DT_ATMEL_SAM0_SPI_SERCOM_3_TXDMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_3_RXDMA
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#define DT_ATMEL_SAM0_SPI_SERCOM_3_RXDMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_4_TXDMA
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#define DT_ATMEL_SAM0_SPI_SERCOM_4_TXDMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_4_RXDMA
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#define DT_ATMEL_SAM0_SPI_SERCOM_4_RXDMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_5_TXDMA
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#define DT_ATMEL_SAM0_SPI_SERCOM_5_TXDMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_5_RXDMA
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#define DT_ATMEL_SAM0_SPI_SERCOM_5_RXDMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_6_TXDMA
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#define DT_ATMEL_SAM0_SPI_SERCOM_6_TXDMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_SPI_SERCOM_7_RXDMA
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#define DT_ATMEL_SAM0_SPI_SERCOM_7_RXDMA 0xFF
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#endif
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#define SPI_SAM0_DMA_CHANNELS(n) \
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.tx_dma_request = SERCOM##n##_DMAC_ID_TX, \
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.tx_dma_channel = DT_ATMEL_SAM0_SPI_SERCOM_##n##_TXDMA, \
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.rx_dma_request = SERCOM##n##_DMAC_ID_RX, \
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.rx_dma_channel = DT_ATMEL_SAM0_SPI_SERCOM_##n##_RXDMA
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#else
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#else
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#define SPI_SAM0_DMA_CHANNELS(n)
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#define SPI_SAM0_DMA_CHANNELS(n)
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#endif
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#endif
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#define SPI_SAM0_SERCOM_PADS(n) \
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#define SPI_SAM0_SERCOM_PADS(n) \
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SERCOM_SPI_CTRLA_DIPO(DT_ATMEL_SAM0_SPI_SERCOM_##n##_DIPO) | \
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SERCOM_SPI_CTRLA_DIPO(DT_INST_PROP(n, dipo)) | \
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SERCOM_SPI_CTRLA_DOPO(DT_ATMEL_SAM0_SPI_SERCOM_##n##_DOPO)
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SERCOM_SPI_CTRLA_DOPO(DT_INST_PROP(n, dopo))
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#ifdef MCLK
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#ifdef MCLK
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#define SPI_SAM0_DEFINE_CONFIG(n) \
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#define SPI_SAM0_DEFINE_CONFIG(n) \
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static const struct spi_sam0_config spi_sam0_config_##n = { \
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static const struct spi_sam0_config spi_sam0_config_##n = { \
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.regs = (SercomSpi *)DT_ATMEL_SAM0_SPI_SERCOM_##n##_BASE_ADDRESS,\
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.regs = (SercomSpi *)DT_INST_REG_ADDR(n), \
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.mclk = MCLK_SERCOM##n, \
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.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n), \
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.mclk_mask = MCLK_SERCOM##n##_MASK, \
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.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
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.gclk_core_id = SERCOM##n##_GCLK_ID_CORE, \
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.gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
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.pads = SPI_SAM0_SERCOM_PADS(n) \
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.pads = SPI_SAM0_SERCOM_PADS(n) \
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}
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}
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#else
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#else
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#define SPI_SAM0_DEFINE_CONFIG(n) \
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#define SPI_SAM0_DEFINE_CONFIG(n) \
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static const struct spi_sam0_config spi_sam0_config_##n = { \
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static const struct spi_sam0_config spi_sam0_config_##n = { \
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.regs = (SercomSpi *)DT_ATMEL_SAM0_SPI_SERCOM_##n##_BASE_ADDRESS,\
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.regs = (SercomSpi *)DT_INST_REG_ADDR(n), \
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.pm_apbcmask = PM_APBCMASK_SERCOM##n, \
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.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit)), \
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.gclk_clkctrl_id = GCLK_CLKCTRL_ID_SERCOM##n##_CORE, \
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.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),\
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.pads = SPI_SAM0_SERCOM_PADS(n), \
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.pads = SPI_SAM0_SERCOM_PADS(n), \
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SPI_SAM0_DMA_CHANNELS(n) \
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SPI_SAM0_DMA_CHANNELS(n) \
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}
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}
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#endif /* MCLK */
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#endif /* MCLK */
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#define SPI_SAM0_DEVICE_INIT(n) \
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#define SPI_SAM0_DEVICE_INIT(n) \
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SPI_SAM0_DEFINE_CONFIG(n); \
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SPI_SAM0_DEFINE_CONFIG(n); \
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static struct spi_sam0_data spi_sam0_dev_data_##n = { \
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static struct spi_sam0_data spi_sam0_dev_data_##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_sam0_dev_data_##n, ctx), \
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SPI_CONTEXT_INIT_LOCK(spi_sam0_dev_data_##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_sam0_dev_data_##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_sam0_dev_data_##n, ctx), \
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}; \
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}; \
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DEVICE_AND_API_INIT(spi_sam0_##n, \
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DEVICE_AND_API_INIT(spi_sam0_##n, \
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DT_ATMEL_SAM0_SPI_SERCOM_##n##_LABEL, \
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DT_INST_LABEL(n), \
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&spi_sam0_init, &spi_sam0_dev_data_##n, \
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&spi_sam0_init, &spi_sam0_dev_data_##n, \
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&spi_sam0_config_##n, POST_KERNEL, \
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&spi_sam0_config_##n, POST_KERNEL, \
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CONFIG_SPI_INIT_PRIORITY, &spi_sam0_driver_api)
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CONFIG_SPI_INIT_PRIORITY, \
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&spi_sam0_driver_api)
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#if DT_ATMEL_SAM0_SPI_SERCOM_0_BASE_ADDRESS
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DT_INST_FOREACH(SPI_SAM0_DEVICE_INIT)
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SPI_SAM0_DEVICE_INIT(0);
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#endif
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#if DT_ATMEL_SAM0_SPI_SERCOM_1_BASE_ADDRESS
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SPI_SAM0_DEVICE_INIT(1);
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#endif
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#if DT_ATMEL_SAM0_SPI_SERCOM_2_BASE_ADDRESS
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SPI_SAM0_DEVICE_INIT(2);
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#endif
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#if DT_ATMEL_SAM0_SPI_SERCOM_3_BASE_ADDRESS
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SPI_SAM0_DEVICE_INIT(3);
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#endif
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#if DT_ATMEL_SAM0_SPI_SERCOM_4_BASE_ADDRESS
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SPI_SAM0_DEVICE_INIT(4);
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#endif
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#if DT_ATMEL_SAM0_SPI_SERCOM_5_BASE_ADDRESS
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SPI_SAM0_DEVICE_INIT(5);
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#endif
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#if DT_ATMEL_SAM0_SPI_SERCOM_6_BASE_ADDRESS
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SPI_SAM0_DEVICE_INIT(6);
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#endif
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#if DT_ATMEL_SAM0_SPI_SERCOM_7_BASE_ADDRESS
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SPI_SAM0_DEVICE_INIT(7);
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#endif
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@ -27,12 +27,19 @@ properties:
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required: true
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required: true
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description: Data Out Pinout
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description: Data Out Pinout
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rxdma:
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dmas:
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type: int
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description: |
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required: false
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Optional TX & RX dma specifiers. Each specifier will have a phandle
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description: Receive DMA channel
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reference to the dmac controller, the channel number, and peripheral
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trigger source.
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txdma:
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For example dmas for TX, RX on SERCOM3
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type: int
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dmas = <&dmac 0 0xb>, <&dmac 1 0xa>;
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required: false
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description: Transmit DMA channel
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dma-names:
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description: |
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Required if the dmas property exists. This should be "tx" and "rx"
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to match the dmas property.
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For example
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dma-names = "tx", "rx";
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