soc/xtensa: Misc. checkpatch fixups

Code style fixes.  Kept separate from the original changes to permit
easier rebasing.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>

boards/xtensa/up_squared_adsp/tools/adsplog.py

@@ -2,6 +2,7 @@
 #
 # Copyright (c) 2020 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
+
 import sys
 import time
 import struct
@@ -73,8 +74,8 @@ while True:
                 break
             msgbytes.append(b)
         msg = bytearray(len(msgbytes))
-        for i in range(len(msgbytes)):
-            msg[i] = msgbytes[i]
+        for i, elem in enumerate(msgbytes):
+            msg[i] = elem
 
         sys.stdout.write(msg.decode(encoding="utf-8", errors="ignore"))
         next_slot = int((next_slot + 1) % (MAP_SIZE / SLOT_SIZE))

dts/xtensa/intel/intel_byt_adsp.dtsi

@@ -33,7 +33,6 @@
 	};
 
 	soc {
-	
 		core_intc: core_intc@0 {
 			compatible = "xtensa,core-intc";
 			reg = <0x00 0x400>;

kernel/thread.c

@@ -567,7 +567,8 @@ char *z_setup_new_thread(struct k_thread *new_thread,
 
 #ifdef KERNEL_COHERENCE
 	/* Check that the thread object is safe, but that the stack is
-         * still cached! */
+	 * still cached!
+	 */
 	__ASSERT_NO_MSG(arch_mem_coherent(new_thread));
 	__ASSERT_NO_MSG(!arch_mem_coherent(stack));
 #endif

soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h

@@ -213,7 +213,8 @@
 /* SRAM window 0 FW "registers" */
 #define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE      0x14
 #define SRAM_REG_FW_END \
-        (SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4)
+	(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + \
+	 (PLATFORM_CORE_COUNT - 1) * 0x4)
 
 /* Host page size */
 #define HOST_PAGE_SIZE		4096

soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h

@@ -1,5 +1,4 @@
 /* SPDX-License-Identifier: Apache-2.0
-
  *
  * Copyright(c) 2017 Intel Corporation. All rights reserved.
  *

soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h

@@ -1,4 +1,4 @@
-s/*
+/*
  * Copyright (c) 2019 Intel Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -213,7 +213,8 @@ s/*
 /* SRAM window 0 FW "registers" */
 #define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE      0x14
 #define SRAM_REG_FW_END \
-        (SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4)
+	(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + \
+	 (PLATFORM_CORE_COUNT - 1) * 0x4)
 
 /* Host page size */
 #define HOST_PAGE_SIZE		4096

soc/xtensa/intel_adsp/common/bootloader/boot_loader.c

@@ -195,7 +195,7 @@ static int32_t hp_sram_pm_banks(uint32_t banks)
 		ebb_avail_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0);
 		ebb_avail_mask1 = (uint32_t)GENMASK(total_banks_count -
 		EBB_SEGMENT_SIZE - 1, 0);
-	} else{
+	} else {
 		ebb_avail_mask0 = (uint32_t)GENMASK(total_banks_count - 1,
 		0);
 		ebb_avail_mask1 = 0;
@@ -206,7 +206,7 @@ static int32_t hp_sram_pm_banks(uint32_t banks)
 		ebb_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0);
 		ebb_mask1 = (uint32_t)GENMASK(banks - EBB_SEGMENT_SIZE - 1,
 		0);
-	} else{
+	} else {
 		/* assumption that ebb_in_use is > 0 */
 		ebb_mask0 = (uint32_t)GENMASK(banks - 1, 0);
 		ebb_mask1 = 0;

soc/xtensa/intel_adsp/common/fix_elf_addrs.py

@@ -32,7 +32,7 @@ with open(elffile, "rb") as fd:
     elf = ELFFile(fd)
     for s in elf.iter_sections():
         addr = s.header.sh_addr
-        if addr >= 0x80000000 and addr < 0xa0000000:
+        if 0x80000000 <= addr < 0xa0000000:
             print(f"fix_elf_addrs.py: Moving section {s.name} to cached SRAM region")
             fixup.append(s.name)
 

soc/xtensa/intel_adsp/common/printk_out.c

@@ -30,7 +30,7 @@
 /* Translates a SRAM pointer into an address of the same memory in the
  * uncached region from 0x80000000-0x9fffffff
  */
-#define UNCACHED_PTR(p) ((void*)(((int)p) & ~0x20000000))
+#define UNCACHED_PTR(p) ((void *)(((int)p) & ~0x20000000))
 
 struct slot_hdr {
 	uint16_t magic;