From a8d54377993cb9f899047cb6c54140f980edcd78 Mon Sep 17 00:00:00 2001 From: Andy Ross Date: Tue, 6 Oct 2020 11:39:48 -0700 Subject: [PATCH] soc/xtensa: Misc. checkpatch fixups Code style fixes. Kept separate from the original changes to permit easier rebasing. Signed-off-by: Andy Ross --- arch/xtensa/include/kernel_arch_func.h | 4 ++-- boards/xtensa/up_squared_adsp/tools/adsplog.py | 5 +++-- dts/xtensa/intel/intel_byt_adsp.dtsi | 3 +-- include/sys/arch_interface.h | 4 ++-- kernel/thread.c | 5 +++-- soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series | 4 ++-- soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h | 8 ++++---- soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h | 3 ++- soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h | 1 - soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h | 4 ++-- soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h | 2 +- soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h | 9 +++++---- soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h | 2 +- soc/xtensa/intel_adsp/cavs_v25/linker.ld | 2 +- soc/xtensa/intel_adsp/common/bootloader/boot_loader.c | 4 ++-- soc/xtensa/intel_adsp/common/fix_elf_addrs.py | 2 +- soc/xtensa/intel_adsp/common/printk_out.c | 2 +- 17 files changed, 33 insertions(+), 31 deletions(-) diff --git a/arch/xtensa/include/kernel_arch_func.h b/arch/xtensa/include/kernel_arch_func.h index 5521416956b..8485969e7ab 100644 --- a/arch/xtensa/include/kernel_arch_func.h +++ b/arch/xtensa/include/kernel_arch_func.h @@ -69,9 +69,9 @@ static inline void arch_switch(void *switch_to, void **switched_from) #ifdef CONFIG_SOC_FAMILY_INTEL_ADSP static inline bool arch_mem_coherent(void *ptr) { - size_t addr = (size_t) ptr; + size_t addr = (size_t) ptr; - return addr >= 0x80000000 && addr < 0xa0000000; + return addr >= 0x80000000 && addr < 0xa0000000; } #endif diff --git a/boards/xtensa/up_squared_adsp/tools/adsplog.py b/boards/xtensa/up_squared_adsp/tools/adsplog.py index f2084ebf13e..8df555cf8e5 100755 --- a/boards/xtensa/up_squared_adsp/tools/adsplog.py +++ b/boards/xtensa/up_squared_adsp/tools/adsplog.py @@ -2,6 +2,7 @@ # # Copyright (c) 2020 Intel Corporation # SPDX-License-Identifier: Apache-2.0 + import sys import time import struct @@ -73,8 +74,8 @@ while True: break msgbytes.append(b) msg = bytearray(len(msgbytes)) - for i in range(len(msgbytes)): - msg[i] = msgbytes[i] + for i, elem in enumerate(msgbytes): + msg[i] = elem sys.stdout.write(msg.decode(encoding="utf-8", errors="ignore")) next_slot = int((next_slot + 1) % (MAP_SIZE / SLOT_SIZE)) diff --git a/dts/xtensa/intel/intel_byt_adsp.dtsi b/dts/xtensa/intel/intel_byt_adsp.dtsi index fd246107e49..384e97ecf7e 100644 --- a/dts/xtensa/intel/intel_byt_adsp.dtsi +++ b/dts/xtensa/intel/intel_byt_adsp.dtsi @@ -33,14 +33,13 @@ }; soc { - core_intc: core_intc@0 { compatible = "xtensa,core-intc"; reg = <0x00 0x400>; interrupt-controller; #interrupt-cells = <3>; }; - + mailbox: mailbox@ff340018 { compatible = "intel,intel-adsp-mailbox"; reg = <0xFF340018 0x30>; diff --git a/include/sys/arch_interface.h b/include/sys/arch_interface.h index 8f96a96d954..a9e8b9a758e 100644 --- a/include/sys/arch_interface.h +++ b/include/sys/arch_interface.h @@ -755,8 +755,8 @@ static inline bool arch_mem_coherent(void *ptr) */ #ifndef CONFIG_KERNEL_COHERENCE static inline void arch_cohere_stacks(struct k_thread *old_thread, - void *old_switch_handle, - struct k_thread *new_thread) + void *old_switch_handle, + struct k_thread *new_thread) { ARG_UNUSED(old_thread); ARG_UNUSED(old_switch_handle); diff --git a/kernel/thread.c b/kernel/thread.c index e1ef8ce72a1..260ecabc74a 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -566,8 +566,9 @@ char *z_setup_new_thread(struct k_thread *new_thread, stack_ptr = setup_thread_stack(new_thread, stack, stack_size); #ifdef KERNEL_COHERENCE - /* Check that the thread object is safe, but that the stack is - * still cached! */ + /* Check that the thread object is safe, but that the stack is + * still cached! + */ __ASSERT_NO_MSG(arch_mem_coherent(new_thread)); __ASSERT_NO_MSG(!arch_mem_coherent(stack)); #endif diff --git a/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series index e9251d64fa0..457a118b743 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series +++ b/soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series @@ -12,7 +12,7 @@ config SOC default "intel_apl_adsp" if SOC_INTEL_CAVS_APL config SMP - default y + default y config MP_NUM_CPUS default 2 @@ -59,7 +59,7 @@ config IPM_CAVS_IDC default y config IPM - default y + default y if LOG diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h index 41c028bae1e..616654b588e 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h @@ -14,8 +14,8 @@ SRAM_DEBUG_SIZE + \ SRAM_TRACE_SIZE) -#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) -#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) +#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) +#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) #ifdef CONFIG_BOOTLOADER_MCUBOOT #define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) @@ -98,8 +98,8 @@ #define IDT_SIZE 0x2000 /* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) -#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) +#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) +#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) /* bootloader */ diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index 81a0649fbf7..d496097b4b6 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -213,7 +213,8 @@ /* SRAM window 0 FW "registers" */ #define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14 #define SRAM_REG_FW_END \ - (SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4) + (SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + \ + (PLATFORM_CORE_COUNT - 1) * 0x4) /* Host page size */ #define HOST_PAGE_SIZE 4096 diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h index 2102883bef1..98787f14c46 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: Apache-2.0 - * * Copyright(c) 2017 Intel Corporation. All rights reserved. * diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index ddb35645312..1a9983b03dc 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -95,8 +95,8 @@ #define IDT_SIZE 0x2000 /* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) -#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) +#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) +#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) /* bootloader */ diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h index 97aeef6adaf..19bf8952410 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h @@ -253,7 +253,7 @@ #define DSP_INIT_IOPO 0x71A68 #define IOPO_DMIC_FLAG BIT(0) -#define IOPO_I2S_FLAG GENMASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8) +#define IOPO_I2S_FLAG GENMASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8) #define DSP_INIT_GENO 0x71A6C #define GENO_MDIVOSEL BIT(1) diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index b5005b9824b..6c448a84189 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -1,4 +1,4 @@ -s/* +/* * Copyright (c) 2019 Intel Corporation * SPDX-License-Identifier: Apache-2.0 */ @@ -95,8 +95,8 @@ s/* #define IDT_SIZE 0x2000 /* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) -#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) +#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) +#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) /* bootloader */ @@ -213,7 +213,8 @@ s/* /* SRAM window 0 FW "registers" */ #define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14 #define SRAM_REG_FW_END \ - (SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4) + (SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + \ + (PLATFORM_CORE_COUNT - 1) * 0x4) /* Host page size */ #define HOST_PAGE_SIZE 4096 diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h index 7356d62aef3..9e1ab07d914 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h @@ -262,7 +262,7 @@ #define DSP_INIT_IOPO 0x71A68 #define IOPO_DMIC_FLAG BIT(0) -#define IOPO_I2S_FLAG GENMASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8) +#define IOPO_I2S_FLAG GENMASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8) #define DSP_INIT_GENO 0x71A6C #define GENO_MDIVOSEL BIT(1) diff --git a/soc/xtensa/intel_adsp/cavs_v25/linker.ld b/soc/xtensa/intel_adsp/cavs_v25/linker.ld index 4fca11562ef..39a4c99b190 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v25/linker.ld @@ -154,7 +154,7 @@ PHDRS static_uuid_entries_phdr PT_NOTE; static_log_entries_phdr PT_NOTE; - + lpsram_mem_phdr PT_LOAD; sram_alt_fw_reset_vec_phdr PT_LOAD; sram_alt_fw_reset_vec_int_phdr PT_LOAD; diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c index 86699b87b16..a2f88ff9b61 100644 --- a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c +++ b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c @@ -195,7 +195,7 @@ static int32_t hp_sram_pm_banks(uint32_t banks) ebb_avail_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0); ebb_avail_mask1 = (uint32_t)GENMASK(total_banks_count - EBB_SEGMENT_SIZE - 1, 0); - } else{ + } else { ebb_avail_mask0 = (uint32_t)GENMASK(total_banks_count - 1, 0); ebb_avail_mask1 = 0; @@ -206,7 +206,7 @@ static int32_t hp_sram_pm_banks(uint32_t banks) ebb_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0); ebb_mask1 = (uint32_t)GENMASK(banks - EBB_SEGMENT_SIZE - 1, 0); - } else{ + } else { /* assumption that ebb_in_use is > 0 */ ebb_mask0 = (uint32_t)GENMASK(banks - 1, 0); ebb_mask1 = 0; diff --git a/soc/xtensa/intel_adsp/common/fix_elf_addrs.py b/soc/xtensa/intel_adsp/common/fix_elf_addrs.py index e7b11185b04..e6a938abe50 100755 --- a/soc/xtensa/intel_adsp/common/fix_elf_addrs.py +++ b/soc/xtensa/intel_adsp/common/fix_elf_addrs.py @@ -32,7 +32,7 @@ with open(elffile, "rb") as fd: elf = ELFFile(fd) for s in elf.iter_sections(): addr = s.header.sh_addr - if addr >= 0x80000000 and addr < 0xa0000000: + if 0x80000000 <= addr < 0xa0000000: print(f"fix_elf_addrs.py: Moving section {s.name} to cached SRAM region") fixup.append(s.name) diff --git a/soc/xtensa/intel_adsp/common/printk_out.c b/soc/xtensa/intel_adsp/common/printk_out.c index 4ce6e9a6430..ddb0cdbdb41 100644 --- a/soc/xtensa/intel_adsp/common/printk_out.c +++ b/soc/xtensa/intel_adsp/common/printk_out.c @@ -30,7 +30,7 @@ /* Translates a SRAM pointer into an address of the same memory in the * uncached region from 0x80000000-0x9fffffff */ -#define UNCACHED_PTR(p) ((void*)(((int)p) & ~0x20000000)) +#define UNCACHED_PTR(p) ((void *)(((int)p) & ~0x20000000)) struct slot_hdr { uint16_t magic;