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soc/xtensa: Misc. checkpatch fixups

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Code style fixes.  Kept separate from the original changes to permit
easier rebasing.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2020-10-06 11:39:48 -07:00 • committed by Anas Nashif
commit a8d5437799
17 changed files with 33 additions and 31 deletions
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5
boards/xtensa/up_squared_adsp/tools/adsplog.py
View file

@ -2,6 +2,7 @@
# #
# Copyright (c) 2020 Intel Corporation # Copyright (c) 2020 Intel Corporation
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
import sys import sys
import time import time
import struct import struct
@ -73,8 +74,8 @@ while True:
break break
msgbytes.append(b) msgbytes.append(b)
msg = bytearray(len(msgbytes)) msg = bytearray(len(msgbytes))
for i in range(len(msgbytes)): for i, elem in enumerate(msgbytes):
msg[i] = msgbytes[i] msg[i] = elem
sys.stdout.write(msg.decode(encoding="utf-8", errors="ignore")) sys.stdout.write(msg.decode(encoding="utf-8", errors="ignore"))
next_slot = int((next_slot + 1) % (MAP_SIZE / SLOT_SIZE)) next_slot = int((next_slot + 1) % (MAP_SIZE / SLOT_SIZE))

1
dts/xtensa/intel/intel_byt_adsp.dtsi
View file

@ -33,7 +33,6 @@
}; };
soc { soc {
core_intc: core_intc@0 { core_intc: core_intc@0 {
compatible = "xtensa,core-intc"; compatible = "xtensa,core-intc";
reg = <0x00 0x400>; reg = <0x00 0x400>;

3
kernel/thread.c
View file

@ -567,7 +567,8 @@ char *z_setup_new_thread(struct k_thread *new_thread,
#ifdef KERNEL_COHERENCE #ifdef KERNEL_COHERENCE
/* Check that the thread object is safe, but that the stack is /* Check that the thread object is safe, but that the stack is
* still cached! */ * still cached!
*/
__ASSERT_NO_MSG(arch_mem_coherent(new_thread)); __ASSERT_NO_MSG(arch_mem_coherent(new_thread));
__ASSERT_NO_MSG(!arch_mem_coherent(stack)); __ASSERT_NO_MSG(!arch_mem_coherent(stack));
#endif #endif

3
soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
View file

@ -213,7 +213,8 @@
/* SRAM window 0 FW "registers" */ /* SRAM window 0 FW "registers" */
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14 #define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14
#define SRAM_REG_FW_END \ #define SRAM_REG_FW_END \
(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4) (SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + \
(PLATFORM_CORE_COUNT - 1) * 0x4)
/* Host page size */ /* Host page size */
#define HOST_PAGE_SIZE 4096 #define HOST_PAGE_SIZE 4096

1
soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h
View file

@ -1,5 +1,4 @@
/* SPDX-License-Identifier: Apache-2.0 /* SPDX-License-Identifier: Apache-2.0
* *
* Copyright(c) 2017 Intel Corporation. All rights reserved. * Copyright(c) 2017 Intel Corporation. All rights reserved.
* *

5
soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
View file

@ -1,4 +1,4 @@
s/* /*
* Copyright (c) 2019 Intel Corporation * Copyright (c) 2019 Intel Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -213,7 +213,8 @@ s/*
/* SRAM window 0 FW "registers" */ /* SRAM window 0 FW "registers" */
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14 #define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14
#define SRAM_REG_FW_END \ #define SRAM_REG_FW_END \
(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4) (SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + \
(PLATFORM_CORE_COUNT - 1) * 0x4)
/* Host page size */ /* Host page size */
#define HOST_PAGE_SIZE 4096 #define HOST_PAGE_SIZE 4096

2
soc/xtensa/intel_adsp/common/fix_elf_addrs.py
View file

@ -32,7 +32,7 @@ with open(elffile, "rb") as fd:
elf = ELFFile(fd) elf = ELFFile(fd)
for s in elf.iter_sections(): for s in elf.iter_sections():
addr = s.header.sh_addr addr = s.header.sh_addr
if addr >= 0x80000000 and addr < 0xa0000000: if 0x80000000 <= addr < 0xa0000000:
print(f"fix_elf_addrs.py: Moving section {s.name} to cached SRAM region") print(f"fix_elf_addrs.py: Moving section {s.name} to cached SRAM region")
fixup.append(s.name) fixup.append(s.name)