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soc/xtensa: Misc. checkpatch fixups

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Code style fixes.  Kept separate from the original changes to permit
easier rebasing.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2020-10-06 11:39:48 -07:00 • committed by Anas Nashif
commit a8d5437799
17 changed files with 33 additions and 31 deletions
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4
soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
View file

@ -195,7 +195,7 @@ static int32_t hp_sram_pm_banks(uint32_t banks)
ebb_avail_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0);
ebb_avail_mask1 = (uint32_t)GENMASK(total_banks_count -
EBB_SEGMENT_SIZE - 1, 0);
} else{
} else {
ebb_avail_mask0 = (uint32_t)GENMASK(total_banks_count - 1,
0);
ebb_avail_mask1 = 0;
@ -206,7 +206,7 @@ static int32_t hp_sram_pm_banks(uint32_t banks)
ebb_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0);
ebb_mask1 = (uint32_t)GENMASK(banks - EBB_SEGMENT_SIZE - 1,
0);
} else{
} else {
/* assumption that ebb_in_use is > 0 */
ebb_mask0 = (uint32_t)GENMASK(banks - 1, 0);
ebb_mask1 = 0;

2
soc/xtensa/intel_adsp/common/fix_elf_addrs.py
View file

@ -32,7 +32,7 @@ with open(elffile, "rb") as fd:
elf = ELFFile(fd)
for s in elf.iter_sections():
addr = s.header.sh_addr
if addr >= 0x80000000 and addr < 0xa0000000:
if 0x80000000 <= addr < 0xa0000000:
print(f"fix_elf_addrs.py: Moving section {s.name} to cached SRAM region")
fixup.append(s.name)

2
soc/xtensa/intel_adsp/common/printk_out.c
View file

@ -30,7 +30,7 @@
/* Translates a SRAM pointer into an address of the same memory in the
* uncached region from 0x80000000-0x9fffffff
*/
#define UNCACHED_PTR(p) ((void*)(((int)p) & ~0x20000000))
#define UNCACHED_PTR(p) ((void *)(((int)p) & ~0x20000000))
struct slot_hdr {
uint16_t magic;