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soc/xtensa: Misc. checkpatch fixups

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Code style fixes.  Kept separate from the original changes to permit
easier rebasing.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2020-10-06 11:39:48 -07:00 • committed by Anas Nashif
commit a8d5437799
17 changed files with 33 additions and 31 deletions
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4
soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series
View file

@ -12,7 +12,7 @@ config SOC
default "intel_apl_adsp" if SOC_INTEL_CAVS_APL
config SMP
default y
default y
config MP_NUM_CPUS
default 2
@ -59,7 +59,7 @@ config IPM_CAVS_IDC
default y
config IPM
default y
default y
if LOG

8
soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
View file

@ -14,8 +14,8 @@
SRAM_DEBUG_SIZE + \
SRAM_TRACE_SIZE)
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#ifdef CONFIG_BOOTLOADER_MCUBOOT
#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
@ -98,8 +98,8 @@
#define IDT_SIZE 0x2000
/* low power ram where DMA buffers are typically placed */
#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
/* bootloader */

3
soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
View file

@ -213,7 +213,8 @@
/* SRAM window 0 FW "registers" */
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14
#define SRAM_REG_FW_END \
(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4)
(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + \
(PLATFORM_CORE_COUNT - 1) * 0x4)
/* Host page size */
#define HOST_PAGE_SIZE 4096

1
soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h
View file

@ -1,5 +1,4 @@
/* SPDX-License-Identifier: Apache-2.0
*
* Copyright(c) 2017 Intel Corporation. All rights reserved.
*

4
soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
View file

@ -95,8 +95,8 @@
#define IDT_SIZE 0x2000
/* low power ram where DMA buffers are typically placed */
#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
/* bootloader */

2
soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h
View file

@ -253,7 +253,7 @@
#define DSP_INIT_IOPO 0x71A68
#define IOPO_DMIC_FLAG BIT(0)
#define IOPO_I2S_FLAG GENMASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8)
#define IOPO_I2S_FLAG GENMASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8)
#define DSP_INIT_GENO 0x71A6C
#define GENO_MDIVOSEL BIT(1)

9
soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
View file

@ -1,4 +1,4 @@
s/*
/*
* Copyright (c) 2019 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
@ -95,8 +95,8 @@ s/*
#define IDT_SIZE 0x2000
/* low power ram where DMA buffers are typically placed */
#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
/* bootloader */
@ -213,7 +213,8 @@ s/*
/* SRAM window 0 FW "registers" */
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14
#define SRAM_REG_FW_END \
(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4)
(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + \
(PLATFORM_CORE_COUNT - 1) * 0x4)
/* Host page size */
#define HOST_PAGE_SIZE 4096

2
soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h
View file

@ -262,7 +262,7 @@
#define DSP_INIT_IOPO 0x71A68
#define IOPO_DMIC_FLAG BIT(0)
#define IOPO_I2S_FLAG GENMASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8)
#define IOPO_I2S_FLAG GENMASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8)
#define DSP_INIT_GENO 0x71A6C
#define GENO_MDIVOSEL BIT(1)

2
soc/xtensa/intel_adsp/cavs_v25/linker.ld
View file

@ -154,7 +154,7 @@ PHDRS
static_uuid_entries_phdr PT_NOTE;
static_log_entries_phdr PT_NOTE;
lpsram_mem_phdr PT_LOAD;
sram_alt_fw_reset_vec_phdr PT_LOAD;
sram_alt_fw_reset_vec_int_phdr PT_LOAD;

4
soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
View file

@ -195,7 +195,7 @@ static int32_t hp_sram_pm_banks(uint32_t banks)
ebb_avail_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0);
ebb_avail_mask1 = (uint32_t)GENMASK(total_banks_count -
EBB_SEGMENT_SIZE - 1, 0);
} else{
} else {
ebb_avail_mask0 = (uint32_t)GENMASK(total_banks_count - 1,
0);
ebb_avail_mask1 = 0;
@ -206,7 +206,7 @@ static int32_t hp_sram_pm_banks(uint32_t banks)
ebb_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0);
ebb_mask1 = (uint32_t)GENMASK(banks - EBB_SEGMENT_SIZE - 1,
0);
} else{
} else {
/* assumption that ebb_in_use is > 0 */
ebb_mask0 = (uint32_t)GENMASK(banks - 1, 0);
ebb_mask1 = 0;

2
soc/xtensa/intel_adsp/common/fix_elf_addrs.py
View file

@ -32,7 +32,7 @@ with open(elffile, "rb") as fd:
elf = ELFFile(fd)
for s in elf.iter_sections():
addr = s.header.sh_addr
if addr >= 0x80000000 and addr < 0xa0000000:
if 0x80000000 <= addr < 0xa0000000:
print(f"fix_elf_addrs.py: Moving section {s.name} to cached SRAM region")
fixup.append(s.name)

2
soc/xtensa/intel_adsp/common/printk_out.c
View file

@ -30,7 +30,7 @@
/* Translates a SRAM pointer into an address of the same memory in the
* uncached region from 0x80000000-0x9fffffff
*/
#define UNCACHED_PTR(p) ((void*)(((int)p) & ~0x20000000))
#define UNCACHED_PTR(p) ((void *)(((int)p) & ~0x20000000))
struct slot_hdr {
uint16_t magic;