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soc: apollo_lake: fix build errors for GPIO due to DTS changes

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The DTS changes introduced in 7ae220c845
changes the naming of GPIO related macros. This updates the usage
of previous macros via DTS fixup.

Fixes #10993

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2018-11-01 10:34:10 -07:00 • committed by Kumar Gala
commit a87a6d82ac
4 changed files with 33 additions and 18 deletions
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13
soc/x86/apollo_lake/dts_fixup.h
View file

@ -16,4 +16,17 @@
#define CONFIG_IOAPIC_BASE_ADDRESS INTEL_IOAPIC_FEC00000_BASE_ADDRESS
#define CONFIG_APL_GPIO_BASE_ADDRESS_0 INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_0
#define CONFIG_APL_GPIO_BASE_ADDRESS_1 INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_1
#define CONFIG_APL_GPIO_BASE_ADDRESS_2 INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_2
#define CONFIG_APL_GPIO_BASE_ADDRESS_3 INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_3
#define CONFIG_APL_GPIO_IRQ INTEL_APL_GPIO_D0C50000_IRQ_0
#define CONFIG_APL_GPIO_IRQ_PRIORITY INTEL_APL_GPIO_D0C50000_IRQ_0_PRIORITY
#define CONFIG_APL_GPIO_IRQ_SENSE INTEL_APL_GPIO_D0C50000_IRQ_0_SENSE
#define CONFIG_APL_GPIO_LABEL INTEL_APL_GPIO_D0C50000_LABEL
#define CONFIG_APL_GPIO_MEM_SIZE_0 INTEL_APL_GPIO_D0C50000_SIZE_0
#define CONFIG_APL_GPIO_MEM_SIZE_1 INTEL_APL_GPIO_D0C50000_SIZE_1
#define CONFIG_APL_GPIO_MEM_SIZE_2 INTEL_APL_GPIO_D0C50000_SIZE_2
#define CONFIG_APL_GPIO_MEM_SIZE_3 oINTEL_APL_GPIO_D0C50000_SIZE_3
/* End of SoC Level DTS fixup file */

16
soc/x86/apollo_lake/soc.c
View file

@ -102,17 +102,17 @@ MMU_BOOT_REGION(CONFIG_I2C_7_BASE_ADDR, 0x1000,
/* for GPIO controller */
#ifdef CONFIG_GPIO_INTEL_APL
MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_0,
INTEL_APL_GPIO_0_SIZE_0,
MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_0,
CONFIG_APL_GPIO_MEM_SIZE_0,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_1,
INTEL_APL_GPIO_0_SIZE_1,
MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_1,
CONFIG_APL_GPIO_MEM_SIZE_1,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_2,
INTEL_APL_GPIO_0_SIZE_2,
MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_2,
CONFIG_APL_GPIO_MEM_SIZE_2,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_3,
INTEL_APL_GPIO_0_SIZE_3,
MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_3,
CONFIG_APL_GPIO_MEM_SIZE_3,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
#endif