From a87a6d82acf08c9183cc45a696a419f979990da6 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Thu, 1 Nov 2018 10:34:10 -0700 Subject: [PATCH] soc: apollo_lake: fix build errors for GPIO due to DTS changes The DTS changes introduced in 7ae220c845194a1c68b258cd4f9b1e63df26eb41 changes the naming of GPIO related macros. This updates the usage of previous macros via DTS fixup. Fixes #10993 Signed-off-by: Daniel Leung --- drivers/gpio/gpio_intel_apl.c | 16 ++++++++-------- .../boards/up_squared/gpio_counter/src/main.c | 6 ++++-- soc/x86/apollo_lake/dts_fixup.h | 13 +++++++++++++ soc/x86/apollo_lake/soc.c | 16 ++++++++-------- 4 files changed, 33 insertions(+), 18 deletions(-) diff --git a/drivers/gpio/gpio_intel_apl.c b/drivers/gpio/gpio_intel_apl.c index 2ff1eb66e56..33a637c3574 100644 --- a/drivers/gpio/gpio_intel_apl.c +++ b/drivers/gpio/gpio_intel_apl.c @@ -430,22 +430,22 @@ static const struct gpio_intel_apl_config gpio_intel_apl_cfg = { .islands = { { /* North island */ - .reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_0, + .reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_0, .num_pins = 78, }, { /* Northwest island */ - .reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_1, + .reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_1, .num_pins = 77, }, { /* West island */ - .reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_2, + .reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_2, .num_pins = 47, }, { /* Southwest island */ - .reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_3, + .reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_3, .num_pins = 43, }, }, @@ -453,7 +453,7 @@ static const struct gpio_intel_apl_config gpio_intel_apl_cfg = { static struct gpio_intel_apl_data gpio_intel_apl_data; -DEVICE_AND_API_INIT(gpio_intel_apl, INTEL_APL_GPIO_0_LABEL, +DEVICE_AND_API_INIT(gpio_intel_apl, CONFIG_APL_GPIO_LABEL, gpio_intel_apl_init, &gpio_intel_apl_data, &gpio_intel_apl_cfg, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -461,9 +461,9 @@ DEVICE_AND_API_INIT(gpio_intel_apl, INTEL_APL_GPIO_0_LABEL, static void gpio_intel_apl_irq_config(struct device *dev) { - IRQ_CONNECT(INTEL_APL_GPIO_0_IRQ_0, INTEL_APL_GPIO_0_IRQ_0_PRIORITY, + IRQ_CONNECT(CONFIG_APL_GPIO_IRQ, CONFIG_APL_GPIO_IRQ_PRIORITY, gpio_intel_apl_isr, DEVICE_GET(gpio_intel_apl), - INTEL_APL_GPIO_0_IRQ_0_SENSE); + CONFIG_APL_GPIO_IRQ_SENSE); - irq_enable(INTEL_APL_GPIO_0_IRQ_0); + irq_enable(CONFIG_APL_GPIO_IRQ); } diff --git a/samples/boards/up_squared/gpio_counter/src/main.c b/samples/boards/up_squared/gpio_counter/src/main.c index d772ab310b0..9b047f3c8a9 100644 --- a/samples/boards/up_squared/gpio_counter/src/main.c +++ b/samples/boards/up_squared/gpio_counter/src/main.c @@ -63,6 +63,8 @@ K_SEM_DEFINE(counter_sem, 0, 1); #define NUM_PINS ARRAY_SIZE(counter_pins) #define MASK (BIT(NUM_PINS) - 1) +#define GPIO_DEV CONFIG_APL_GPIO_LABEL + void button_cb(struct device *gpiodev, struct gpio_callback *cb, u32_t pin) { counter++; @@ -71,13 +73,13 @@ void button_cb(struct device *gpiodev, struct gpio_callback *cb, u32_t pin) void main(void) { - struct device *gpiodev = device_get_binding(INTEL_APL_GPIO_0_LABEL); + struct device *gpiodev = device_get_binding(GPIO_DEV); u32_t val; int i, ret; if (!gpiodev) { printk("ERROR: cannot get device binding for %s\n", - INTEL_APL_GPIO_0_LABEL); + GPIO_DEV); return; } diff --git a/soc/x86/apollo_lake/dts_fixup.h b/soc/x86/apollo_lake/dts_fixup.h index 25dbc69e8bb..3012661f44a 100644 --- a/soc/x86/apollo_lake/dts_fixup.h +++ b/soc/x86/apollo_lake/dts_fixup.h @@ -16,4 +16,17 @@ #define CONFIG_IOAPIC_BASE_ADDRESS INTEL_IOAPIC_FEC00000_BASE_ADDRESS +#define CONFIG_APL_GPIO_BASE_ADDRESS_0 INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_0 +#define CONFIG_APL_GPIO_BASE_ADDRESS_1 INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_1 +#define CONFIG_APL_GPIO_BASE_ADDRESS_2 INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_2 +#define CONFIG_APL_GPIO_BASE_ADDRESS_3 INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_3 +#define CONFIG_APL_GPIO_IRQ INTEL_APL_GPIO_D0C50000_IRQ_0 +#define CONFIG_APL_GPIO_IRQ_PRIORITY INTEL_APL_GPIO_D0C50000_IRQ_0_PRIORITY +#define CONFIG_APL_GPIO_IRQ_SENSE INTEL_APL_GPIO_D0C50000_IRQ_0_SENSE +#define CONFIG_APL_GPIO_LABEL INTEL_APL_GPIO_D0C50000_LABEL +#define CONFIG_APL_GPIO_MEM_SIZE_0 INTEL_APL_GPIO_D0C50000_SIZE_0 +#define CONFIG_APL_GPIO_MEM_SIZE_1 INTEL_APL_GPIO_D0C50000_SIZE_1 +#define CONFIG_APL_GPIO_MEM_SIZE_2 INTEL_APL_GPIO_D0C50000_SIZE_2 +#define CONFIG_APL_GPIO_MEM_SIZE_3 oINTEL_APL_GPIO_D0C50000_SIZE_3 + /* End of SoC Level DTS fixup file */ diff --git a/soc/x86/apollo_lake/soc.c b/soc/x86/apollo_lake/soc.c index 7c171dfe541..8466b533f0a 100644 --- a/soc/x86/apollo_lake/soc.c +++ b/soc/x86/apollo_lake/soc.c @@ -102,17 +102,17 @@ MMU_BOOT_REGION(CONFIG_I2C_7_BASE_ADDR, 0x1000, /* for GPIO controller */ #ifdef CONFIG_GPIO_INTEL_APL -MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_0, - INTEL_APL_GPIO_0_SIZE_0, +MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_0, + CONFIG_APL_GPIO_MEM_SIZE_0, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); -MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_1, - INTEL_APL_GPIO_0_SIZE_1, +MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_1, + CONFIG_APL_GPIO_MEM_SIZE_1, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); -MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_2, - INTEL_APL_GPIO_0_SIZE_2, +MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_2, + CONFIG_APL_GPIO_MEM_SIZE_2, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); -MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_3, - INTEL_APL_GPIO_0_SIZE_3, +MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_3, + CONFIG_APL_GPIO_MEM_SIZE_3, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); #endif