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boards: nxp: add uhc support for frdm_k22f, rt1060, lpc55s69 and lpc55s28

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add uhc related items to dts.
add clock initialization
add BM4 if CONFIG_USB_UHC_NXP_KHCI is enabled
add pin mux
update board related CMakeLists.txt
update sdk-ng CMake to include NXP controller drivers
update west.yml to contain the hal_nxp pr

Signed-off-by: Mark Wang <yichang.wang@nxp.com>
This commit is contained in:
Mark Wang 2024-09-02 22:09:54 +08:00 • committed by Benjamin Cabé
commit a8796ca6ee
23 changed files with 274 additions and 15 deletions
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12
soc/nxp/imxrt/imxrt10xx/soc.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2017-2023 NXP
* Copyright 2017-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -245,8 +245,9 @@ __weak void clock_init(void)
kIOMUXC_GPR_ENET2RefClkMode, true);
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && \
(CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
#if ((DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && \
(CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)) ||\
(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usbh1)) && (CONFIG_UHC_NXP_EHCI)))
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency));
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M,
@ -256,8 +257,9 @@ __weak void clock_init(void)
#endif
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb2)) && \
(CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
#if ((DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb2)) && \
(CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)) ||\
(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usbh2)) && (CONFIG_UHC_NXP_EHCI)))
CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency));
CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M,

3
soc/nxp/imxrt/imxrt6xx/cm33/CMakeLists.txt
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2020, NXP
# Copyright (c) 2020,2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
@ -19,6 +19,7 @@ zephyr_library_include_directories(
zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
zephyr_compile_definitions_ifdef(CONFIG_UDC_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
zephyr_compile_definitions_ifdef(CONFIG_UHC_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
if(CONFIG_FLASH_MCUX_FLEXSPI_XIP)
zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM)

3
soc/nxp/kinetis/k2x/soc.c
View file

@ -3,6 +3,7 @@
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2018 Prevas A/S
* Copyright (c) 2019 Thomas Burdick <thomas.burdick@gmail.com>
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -102,7 +103,7 @@ __weak void clock_init(void)
CLOCK_SetSimConfig(&simConfig);
#if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS
#if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS || CONFIG_UHC_NXP_KHCI
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
#endif

5
soc/nxp/lpc/lpc55xxx/CMakeLists.txt
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2019, NXP
# Copyright (c) 2019,2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
@ -16,9 +16,12 @@ zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER
SECTIONS usb.ld)
zephyr_linker_sources_ifdef(CONFIG_UDC_DRIVER
SECTIONS usb.ld)
zephyr_linker_sources_ifdef(CONFIG_UHC_DRIVER
SECTIONS usb.ld)
zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
zephyr_compile_definitions_ifdef(CONFIG_UDC_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
zephyr_compile_definitions_ifdef(CONFIG_UHC_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
endif()
# CMSIS SystemInit allows us to skip enabling clock to SRAM banks via

46
soc/nxp/lpc/lpc55xxx/soc.c
View file

@ -1,4 +1,4 @@
/* Copyright 2017, 2019-2023 NXP
/* Copyright 2017, 2019-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -26,7 +26,7 @@
#ifdef CONFIG_GPIO_MCUX_LPC
#include <fsl_pint.h>
#endif
#if CONFIG_USB_DC_NXP_LPCIP3511 || CONFIG_UDC_NXP_IP3511
#if CONFIG_USB_DC_NXP_LPCIP3511 || CONFIG_UDC_NXP_IP3511 || CONFIG_UHC_NXP_IP3516HS
#include "usb_phy.h"
#include "usb.h"
#endif
@ -287,6 +287,48 @@ __weak void clock_init(void)
#endif /* CONFIG_USB_DC_NXP_LPCIP3511 */
#if CONFIG_UHC_NXP_OHCI
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(usbhfs), nxp_uhc_ohci, okay)
/* set BOD VBAT level to 1.65V */
POWER_SetBodVbatLevel(kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false);
NVIC_ClearPendingIRQ(USB0_IRQn);
NVIC_ClearPendingIRQ(USB0_NEEDCLK_IRQn);
/*< Turn on USB Phy */
#if defined(CONFIG_SOC_LPC55S36)
POWER_DisablePD(kPDRUNCFG_PD_USBFSPHY);
#else
POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY);
#endif
RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn);
RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);
RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);
RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbfsSrcPll0, 48000000U);
#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM)
memset((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS, 0, FSL_FEATURE_USBHSD_USB_RAM);
#endif
#endif
#endif
#if CONFIG_UHC_NXP_IP3516HS
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(usbhhs), nxp_uhc_ip3516hs, okay)
/*< Turn on USB Phy */
#if !defined(CONFIG_SOC_LPC55S36)
POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
#endif
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, CLK_CLK_IN);
CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUnused, 0U);
USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, CLK_CLK_IN, NULL);
#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM)
memset((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS, 0, FSL_FEATURE_USBHSD_USB_RAM);
#endif
#endif
#endif
DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP)
DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP)