From a86ee2f2afac2c934403ba5a83dd1fcd8d27f3f2 Mon Sep 17 00:00:00 2001 From: Maciej Sobkowski Date: Mon, 3 Jul 2023 15:57:17 +0200 Subject: [PATCH] drivers: serial: pl011: add definitions for CLKEN/CLKSEL registers Add definitions for CLKEN/CLKSEL registers, which are used to control peripheral clock on the variant of the PL011 UART present in Ambiq SoCs. Signed-off-by: Maciej Sobkowski --- drivers/serial/uart_pl011_registers.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/serial/uart_pl011_registers.h b/drivers/serial/uart_pl011_registers.h index 078a6dbe820..7340dd909af 100644 --- a/drivers/serial/uart_pl011_registers.h +++ b/drivers/serial/uart_pl011_registers.h @@ -105,6 +105,16 @@ volatile struct pl011_regs *const get_uart(const struct device *dev) #define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable */ #define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable */ +/* PL011 Control Register - vendor-specific fields */ +#define PL011_CR_AMBIQ_CLKEN BIT(3) /* clock enable */ +#define PL011_CR_AMBIQ_CLKSEL GENMASK(6, 4) /* clock select */ +#define PL011_CR_AMBIQ_CLKSEL_NOCLK 0 +#define PL011_CR_AMBIQ_CLKSEL_24MHZ 1 +#define PL011_CR_AMBIQ_CLKSEL_12MHZ 2 +#define PL011_CR_AMBIQ_CLKSEL_6MHZ 3 +#define PL011_CR_AMBIQ_CLKSEL_3MHZ 4 +#define PL011_CR_AMBIQ_CLKSEL_48MHZ 5 + /* PL011 Interrupt Fifo Level Select Register */ #define PL011_IFLS_RXIFLSEL_M GENMASK(5, 3) #define RXIFLSEL_1_2_FULL 2UL