michaelh/zephyr
1
0
Fork 0
Code Releases Activity

doc: boards: pollux: reformat tables in documentation

Browse source 
Some tables used more than 120 characters per line. This commit compresses
the formatting of the tables in the documentation.

Signed-off-by: Jonas Remmert <j.remmert@phytec.de>
This commit is contained in:
Jonas Remmert 2024-06-24 11:25:51 +02:00 • committed by Anas Nashif
commit a79b9a369c
1 changed files with 39 additions and 39 deletions
Download patch file Download diff file Expand all files Collapse all files

46
boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst
View file

@ -56,23 +56,23 @@ Supported Features
The Zephyr mimx8mp_phyboard_polis board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
+-----------+------------+------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
+===========+============+====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
+-----------+------------+------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
+-----------+------------+------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
+-----------+------------+------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
+-----------+------------+------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
+-----------+------------+------------------------------------+
| GPIO | on-chip | GPIO output |
| | | GPIO input |
+-----------+------------+-------------------------------------+
+-----------+------------+------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig`.
@ -91,15 +91,15 @@ The following Compontens are tested and working correctly.
UART
----
+---------------+-----------------+-----------------------------------+
+-----------------+----------+----------------------------+
| Board Name | SoM Name | Usage |
+===============+=================+===================================+
| Debug USB(A53)| UART1 | UART Debug Console via USB |
+---------------+-----------------+-----------------------------------+
| Wo WiFi Module| UART3 | UART to WiFi/BLE Module |
+---------------+-----------------+-----------------------------------+
| Debug USB(M4) | UART4 | UART Debug Console via USB |
+---------------+-----------------+-----------------------------------+
+=================+==========+============================+
| Debug USB (A53) | UART1 | UART Debug Console via USB |
+-----------------+----------+----------------------------+
| Wo WiFi Module | UART3 | UART to WiFi/BLE Module |
+-----------------+----------+----------------------------+
| Debug USB (M7) | UART4 | UART Debug Console via USB |
+-----------------+----------+----------------------------+
.. note::
Please note, that the, to UART3 connected, Wifi/BLE Module isn't working with
@ -130,19 +130,19 @@ enable remoteproc support.
The M7 can use up to 3 different RAMs (currently, only two configurations are
supported: ITCM and DDR). These are the memory mapping for A53 and M7:
+------------+-------------------------+------------------------+-----------------------+----------------------+
+---------+-----------------------+------------------------+-----------------------+-------+
| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size |
+============+=========================+========================+=======================+======================+
+=========+=======================+========================+=======================+=======+
| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
+---------+-----------------------+------------------------+-----------------------+-------+
| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
+---------+-----------------------+------------------------+-----------------------+-------+
| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
+---------+-----------------------+------------------------+-----------------------+-------+
| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
+---------+-----------------------+------------------------+-----------------------+-------+
| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB |
+------------+-------------------------+------------------------+-----------------------+----------------------+
+---------+-----------------------+------------------------+-----------------------+-------+
For more information about memory mapping see the
`i.MX 8M Plus Applications Processor Reference Manual`_ (section 2.1 to 2.3)