From a61290e1a337dfdd4baceb63e6dac8eb96693629 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sun, 10 Nov 2019 17:43:26 +0000 Subject: [PATCH] arch: arm64: Add support for qemu_cortex_a53 board This patch introduces support for the qemu_cortex_a53 board emulated using QEMU (virt platform) adding SoC, board and DTS files. | ./scripts/sanitycheck -p qemu_cortex_a53 | | Total complete: 190/ 190 100% skipped: 40, failed: 0 | 150 of 150 tests passed (100.00%), 0 failed, | 40 skipped with 0 warnings in 580.93 seconds Signed-off-by: Carlo Caione --- CODEOWNERS | 4 + boards/arm/qemu_cortex_a53/Kconfig.board | 8 ++ boards/arm/qemu_cortex_a53/Kconfig.defconfig | 12 ++ boards/arm/qemu_cortex_a53/board.cmake | 14 +++ boards/arm/qemu_cortex_a53/doc/index.rst | 110 ++++++++++++++++++ .../qemu_cortex_a53/doc/qemu_cortex_a53.png | Bin 0 -> 10333 bytes .../arm/qemu_cortex_a53/qemu_cortex_a53.dts | 26 +++++ .../arm/qemu_cortex_a53/qemu_cortex_a53.yaml | 19 +++ .../qemu_cortex_a53/qemu_cortex_a53_defconfig | 20 ++++ dts/arm/armv8-a.dtsi | 16 +++ dts/arm/qemu-virt/qemu-virt-a53.dtsi | 72 ++++++++++++ dts/bindings/cpu/arm,cortex-a53.yaml | 9 ++ soc/arm/qemu_cortex_a53/CMakeLists.txt | 2 + soc/arm/qemu_cortex_a53/Kconfig.defconfig | 35 ++++++ soc/arm/qemu_cortex_a53/Kconfig.soc | 9 ++ soc/arm/qemu_cortex_a53/dts_fixup.h | 10 ++ soc/arm/qemu_cortex_a53/linker.ld | 8 ++ soc/arm/qemu_cortex_a53/soc.h | 19 +++ 18 files changed, 393 insertions(+) create mode 100644 boards/arm/qemu_cortex_a53/Kconfig.board create mode 100644 boards/arm/qemu_cortex_a53/Kconfig.defconfig create mode 100644 boards/arm/qemu_cortex_a53/board.cmake create mode 100644 boards/arm/qemu_cortex_a53/doc/index.rst create mode 100644 boards/arm/qemu_cortex_a53/doc/qemu_cortex_a53.png create mode 100644 boards/arm/qemu_cortex_a53/qemu_cortex_a53.dts create mode 100644 boards/arm/qemu_cortex_a53/qemu_cortex_a53.yaml create mode 100644 boards/arm/qemu_cortex_a53/qemu_cortex_a53_defconfig create mode 100644 dts/arm/armv8-a.dtsi create mode 100644 dts/arm/qemu-virt/qemu-virt-a53.dtsi create mode 100644 dts/bindings/cpu/arm,cortex-a53.yaml create mode 100644 soc/arm/qemu_cortex_a53/CMakeLists.txt create mode 100644 soc/arm/qemu_cortex_a53/Kconfig.defconfig create mode 100644 soc/arm/qemu_cortex_a53/Kconfig.soc create mode 100644 soc/arm/qemu_cortex_a53/dts_fixup.h create mode 100644 soc/arm/qemu_cortex_a53/linker.ld create mode 100644 soc/arm/qemu_cortex_a53/soc.h diff --git a/CODEOWNERS b/CODEOWNERS index ba0950f9672..ac0590887e1 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -31,6 +31,7 @@ /soc/arm/bcm*/ @sbranden /soc/arm/nxp*/ @MaureenHelm /soc/arm/nordic_nrf/ @ioannisg +/soc/arm/qemu_cortex_a53/ @carlocaione /soc/arm/st_stm32/ @erwango /soc/arm/st_stm32/stm32f4/ @rsalveti @idlethread /soc/arm/st_stm32/stm32mp1/ @arnopo @@ -77,6 +78,7 @@ /boards/arm/nrf*/ @carlescufi @lemrey @ioannisg /boards/arm/nucleo*/ @erwango /boards/arm/nucleo_f401re/ @rsalveti @idlethread +/boards/arm/qemu_cortex_a53/ @carlocaione /boards/arm/qemu_cortex_m*/ @ioannisg /boards/arm/sam4s_xplained/ @fallrisk /boards/arm/v2m_beetle/ @fvincenzo @@ -210,6 +212,7 @@ /dts/arm/atmel/samr21.dtsi @benpicco /dts/arm/atmel/sam*5*.dtsi @benpicco /dts/arm/broadcom/ @sbranden +/dts/arm/qemu-virt/ @carlocaione /dts/arm/st/ @erwango /dts/arm/ti/cc13?2* @bwitherspoon /dts/arm/ti/cc26?2* @bwitherspoon @@ -226,6 +229,7 @@ /dts/riscv/riscv32-fe310.dtsi @nategraff-sifive /dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda /dts/arm/armv7-r.dtsi @bbolen +/dts/arm/armv8-a.dtsi @carlocaione /dts/arm/xilinx/ @bbolen /dts/xtensa/xtensa.dtsi @ydamigos /dts/bindings/ @galak diff --git a/boards/arm/qemu_cortex_a53/Kconfig.board b/boards/arm/qemu_cortex_a53/Kconfig.board new file mode 100644 index 00000000000..1f771400082 --- /dev/null +++ b/boards/arm/qemu_cortex_a53/Kconfig.board @@ -0,0 +1,8 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_A53 + bool "Cortex-A53 Emulation (QEMU)" + depends on SOC_QEMU_CORTEX_A53 + select ARM64 + select QEMU_TARGET diff --git a/boards/arm/qemu_cortex_a53/Kconfig.defconfig b/boards/arm/qemu_cortex_a53/Kconfig.defconfig new file mode 100644 index 00000000000..cd96283bbc8 --- /dev/null +++ b/boards/arm/qemu_cortex_a53/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_CORTEX_A53 + +config BUILD_OUTPUT_BIN + default n + +config BOARD + default "qemu_cortex_a53" + +endif # BOARD_QEMU_CORTEX_A53 diff --git a/boards/arm/qemu_cortex_a53/board.cmake b/boards/arm/qemu_cortex_a53/board.cmake new file mode 100644 index 00000000000..6faadb93e5e --- /dev/null +++ b/boards/arm/qemu_cortex_a53/board.cmake @@ -0,0 +1,14 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +set(EMU_PLATFORM qemu) +set(QEMU_ARCH aarch64) + +set(QEMU_CPU_TYPE_${ARCH} cortex-a53) +set(QEMU_FLAGS_${ARCH} + -cpu ${QEMU_CPU_TYPE_${ARCH}} + -nographic + -machine virt + ) + +board_set_debugger_ifnset(qemu) diff --git a/boards/arm/qemu_cortex_a53/doc/index.rst b/boards/arm/qemu_cortex_a53/doc/index.rst new file mode 100644 index 00000000000..ee4a72b2604 --- /dev/null +++ b/boards/arm/qemu_cortex_a53/doc/index.rst @@ -0,0 +1,110 @@ +.. _qemu_cortex_a53: + +ARM Cortex-A53 Emulation (QEMU) +############################### + +Overview +******** + +This board configuration will use QEMU to emulate a generic Cortex-A53 hardware +platform. + +.. figure:: qemu_cortex_a53.png + :width: 600px + :align: center + :alt: Qemu + + Qemu (Credit: qemu.org) + +This configuration provides support for an ARM Cortex-A53 CPU and these +devices: + +* GIC-400 interrupt controller +* ARM architected timer +* PL011 UART controller + +Hardware +******** +Supported Features +================== + +The following hardware features are supported: + ++--------------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++==============+============+======================+ +| GIC | on-chip | interrupt controller | ++--------------+------------+----------------------+ +| PL011 UART | on-chip | serial port | ++--------------+------------+----------------------+ +| ARM TIMER | on-chip | system clock | ++--------------+------------+----------------------+ + +The kernel currently does not support other hardware features on this platform. + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 62.5 MHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART0. + +Known Problems or Limitations +============================== + +The following platform features are unsupported: + +* Writing to the hardware's flash memory + + +Programming and Debugging +************************* + +Use this configuration to run basic Zephyr applications and kernel tests in the QEMU +emulated environment, for example, with the :ref:`synchronization_sample`: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: qemu_cortex_a53 + :goals: run + +This will build an image with the synchronization sample app, boot it using +QEMU, and display the following console output: + +.. code-block:: console + + ***** Booting Zephyr OS build zephyr-v2.0.0-1657-g99d310da48e5 ***** + threadA: Hello World from qemu_cortex_a53! + threadB: Hello World from qemu_cortex_a53! + threadA: Hello World from qemu_cortex_a53! + threadB: Hello World from qemu_cortex_a53! + threadA: Hello World from qemu_cortex_a53! + threadB: Hello World from qemu_cortex_a53! + threadA: Hello World from qemu_cortex_a53! + threadB: Hello World from qemu_cortex_a53! + +Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. + +Debugging +========= + +Refer to the detailed overview about :ref:`application_debugging`. + +Networking +========== + +References +********** + +1. (ID050815) ARM® Cortex®-A Series - Programmer’s Guide for ARMv8-A +2. (ID070919) Arm® Architecture Reference Manual - Armv8, for Armv8-A architecture profile +3. (ARM DAI 0527A) Application Note Bare-metal Boot Code for ARMv8-A Processors +4. AArch64 Exception and Interrupt Handling +5. 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clock-frequency = <24000000>; +}; diff --git a/boards/arm/qemu_cortex_a53/qemu_cortex_a53.yaml b/boards/arm/qemu_cortex_a53/qemu_cortex_a53.yaml new file mode 100644 index 00000000000..6fb367ae03e --- /dev/null +++ b/boards/arm/qemu_cortex_a53/qemu_cortex_a53.yaml @@ -0,0 +1,19 @@ +identifier: qemu_cortex_a53 +name: QEMU Emulation for Cortex-A53 +type: qemu +simulation: qemu +arch: arm +toolchain: + - cross-compile +ram: 128 +testing: + ignore_tags: + - cmsis_rtos + - console + - drivers + - interrupt + - logging + - net + - nfc + - shell + - tracing diff --git a/boards/arm/qemu_cortex_a53/qemu_cortex_a53_defconfig b/boards/arm/qemu_cortex_a53/qemu_cortex_a53_defconfig new file mode 100644 index 00000000000..903cbed60b8 --- /dev/null +++ b/boards/arm/qemu_cortex_a53/qemu_cortex_a53_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_SOC_QEMU_CORTEX_A53=y +CONFIG_BOARD_QEMU_CORTEX_A53=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_XIP=n + +# QEMU settings +CONFIG_SRAM_BASE_ADDRESS=0x40000000 +CONFIG_SRAM_SIZE=131072 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_PL011=y +CONFIG_UART_PL011_PORT0=y diff --git a/dts/arm/armv8-a.dtsi b/dts/arm/armv8-a.dtsi new file mode 100644 index 00000000000..a7503c6eaf6 --- /dev/null +++ b/dts/arm/armv8-a.dtsi @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2019 Carlo Caione + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "skeleton.dtsi" + +/ { + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + }; +}; diff --git a/dts/arm/qemu-virt/qemu-virt-a53.dtsi b/dts/arm/qemu-virt/qemu-virt-a53.dtsi new file mode 100644 index 00000000000..62cdc1aa274 --- /dev/null +++ b/dts/arm/qemu-virt/qemu-virt-a53.dtsi @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2019 Carlo Caione + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Derived from DTS extracted with: + * + * qemu-system-aarch64 -machine virt -cpu cortex-a53 -nographic + * -machine dumpdtb=virt.dtb + * + * dtc -I dtb -O dts virt.dtb + */ + +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0>; + }; + }; + + soc { + interrupt-parent = <&gic>; + + gic: interrupt-controller@8000000 { + compatible = "arm,gic"; + reg = <0x8000000 0x10000>, + <0x8010000 0x10000>; + interrupt-controller; + #interrupt-cells = <4>; + label = "GIC"; + status = "okay"; + }; + + uart0: uart@9000000 { + compatible = "arm,pl011"; + reg = <0x9000000 0x1000>; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_0"; + label = "UART_0"; + }; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_K(64)>; + }; + + arch_timer: timer { + compatible = "arm,arm-timer"; + interrupts = , + , + , + ; + label = "arch_timer"; + }; + }; +}; diff --git a/dts/bindings/cpu/arm,cortex-a53.yaml b/dts/bindings/cpu/arm,cortex-a53.yaml new file mode 100644 index 00000000000..515d906b44d --- /dev/null +++ b/dts/bindings/cpu/arm,cortex-a53.yaml @@ -0,0 +1,9 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +description: > + This is a representation of ARM Cortex-A53 CPU. + +compatible: "arm,cortex-a53" + +include: cpu.yaml diff --git a/soc/arm/qemu_cortex_a53/CMakeLists.txt b/soc/arm/qemu_cortex_a53/CMakeLists.txt new file mode 100644 index 00000000000..326eeaff2c2 --- /dev/null +++ b/soc/arm/qemu_cortex_a53/CMakeLists.txt @@ -0,0 +1,2 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 diff --git a/soc/arm/qemu_cortex_a53/Kconfig.defconfig b/soc/arm/qemu_cortex_a53/Kconfig.defconfig new file mode 100644 index 00000000000..d9990fa6c19 --- /dev/null +++ b/soc/arm/qemu_cortex_a53/Kconfig.defconfig @@ -0,0 +1,35 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +if SOC_QEMU_CORTEX_A53 + +config SOC + default "qemu_cortex_a53" + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + default 220 + +config 2ND_LVL_ISR_TBL_OFFSET + default 1 + +config MAX_IRQ_PER_AGGREGATOR + default 219 + +config NUM_2ND_LEVEL_AGGREGATORS + default 1 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 62500000 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +endif # SOC_QEMU_CORTEX_A53 diff --git a/soc/arm/qemu_cortex_a53/Kconfig.soc b/soc/arm/qemu_cortex_a53/Kconfig.soc new file mode 100644 index 00000000000..9a23c654790 --- /dev/null +++ b/soc/arm/qemu_cortex_a53/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_CORTEX_A53 + bool "QEMU virt platform (cortex-a53)" + select CPU_CORTEX_A53 + select GIC_V2 + select MULTI_LEVEL_INTERRUPTS + select 2ND_LEVEL_INTERRUPTS diff --git a/soc/arm/qemu_cortex_a53/dts_fixup.h b/soc/arm/qemu_cortex_a53/dts_fixup.h new file mode 100644 index 00000000000..f6720cfe12a --- /dev/null +++ b/soc/arm/qemu_cortex_a53/dts_fixup.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2019 Carlo Caione + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_PL011_PORT0_BASE_ADDRESS DT_ARM_PL011_9000000_BASE_ADDRESS +#define DT_PL011_PORT0_NAME DT_ARM_PL011_9000000_LABEL +#define DT_PL011_PORT0_CLOCK_FREQUENCY DT_ARM_PL011_9000000_CLOCK_FREQUENCY +#define DT_PL011_PORT0_BAUD_RATE DT_ARM_PL011_9000000_CURRENT_SPEED diff --git a/soc/arm/qemu_cortex_a53/linker.ld b/soc/arm/qemu_cortex_a53/linker.ld new file mode 100644 index 00000000000..fd1bad9e1d6 --- /dev/null +++ b/soc/arm/qemu_cortex_a53/linker.ld @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2019 Carlo Caione + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include diff --git a/soc/arm/qemu_cortex_a53/soc.h b/soc/arm/qemu_cortex_a53/soc.h new file mode 100644 index 00000000000..889f634fe3e --- /dev/null +++ b/soc/arm/qemu_cortex_a53/soc.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2019 Carlo Caione + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#ifndef _SOC_H_ +#define _SOC_H_ + +#include + +#ifndef _ASMLANGUAGE + +#include + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC_H_ */