From a54a52b0854032b1d296ec16456971b2c8e78859 Mon Sep 17 00:00:00 2001
From: Evan Perry Grove <evan@4grove.com>
Date: Fri, 8 Dec 2023 14:51:37 -0600
Subject: [PATCH] dts: arm: Add support for STM32F722 SoC

The STM32F722 is similar to the STM32F723, but lacks the latter's
more advanced USB PHY. Otherwise, they are virtually identical.

Signed-off-by: Evan Perry Grove <evan@4grove.com>
---
 dts/arm/st/f7/stm32f722.dtsi                  | 53 +++++++++++++++++++
 dts/arm/st/f7/stm32f722Xe.dtsi                | 18 +++++++
 dts/arm/st/f7/stm32f723.dtsi                  | 41 +-------------
 .../stm32f7/Kconfig.defconfig.stm32f722xx     | 15 ++++++
 soc/arm/st_stm32/stm32f7/Kconfig.soc          |  4 ++
 5 files changed, 91 insertions(+), 40 deletions(-)
 create mode 100644 dts/arm/st/f7/stm32f722.dtsi
 create mode 100644 dts/arm/st/f7/stm32f722Xe.dtsi
 create mode 100644 soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f722xx

diff --git a/dts/arm/st/f7/stm32f722.dtsi b/dts/arm/st/f7/stm32f722.dtsi
new file mode 100644
index 00000000000..172f1d8e32b
--- /dev/null
+++ b/dts/arm/st/f7/stm32f722.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2023 Evan Perry Grove
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f7/stm32f7.dtsi>
+
+/ {
+	/* 16KB ITCM @ 0x0, 64KB DTCM @ 0x20000000,
+	 * 176KB SRAM1 @ 0x20010000, 16KB SRAM2 @ 0x2003C00
+	 */
+
+	sram0: memory@20010000 {
+		compatible = "mmio-sram";
+		reg = <0x20010000 DT_SIZE_K(192)>;
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "zephyr,memory-region", "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	itcm: memory@0 {
+		compatible = "zephyr,memory-region", "arm,itcm";
+		reg = <0x00000000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "ITCM";
+	};
+
+	soc {
+		compatible = "st,stm32f722", "st,stm32f7", "simple-bus";
+
+		sdmmc2: sdmmc@40011c00 {
+			compatible = "st,stm32-sdmmc";
+			reg = <0x40011c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>,
+				<&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
+			resets = <&rctl STM32_RESET(APB2, 7U)>;
+			interrupts = <103 0>;
+			status = "disabled";
+		};
+	};
+
+	die_temp: dietemp {
+		ts-cal1-addr = <0x1FF07A2C>;
+		ts-cal2-addr = <0x1FF07A2E>;
+	};
+
+	vref: vref {
+		vrefint-cal-addr = <0x1FF07A2A>;
+	};
+};
diff --git a/dts/arm/st/f7/stm32f722Xe.dtsi b/dts/arm/st/f7/stm32f722Xe.dtsi
new file mode 100644
index 00000000000..79491e4008b
--- /dev/null
+++ b/dts/arm/st/f7/stm32f722Xe.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2023 Evan Perry Grove
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f7/stm32f722.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f7/stm32f723.dtsi b/dts/arm/st/f7/stm32f723.dtsi
index 2b2031d89b5..f8b5448a788 100644
--- a/dts/arm/st/f7/stm32f723.dtsi
+++ b/dts/arm/st/f7/stm32f723.dtsi
@@ -4,28 +4,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <st/f7/stm32f7.dtsi>
+#include <st/f7/stm32f722.dtsi>
 
 / {
-	/* 64KB DTCM @ 0x20000000, 176KB SRAM1 @ 0x20010000, 16KB SRAM2 @ 0x2003C00 */
-
-	sram0: memory@20010000 {
-		compatible = "mmio-sram";
-		reg = <0x20010000 DT_SIZE_K(192)>;
-	};
-
-	dtcm: memory@20000000 {
-		compatible = "zephyr,memory-region", "arm,dtcm";
-		reg = <0x20000000 DT_SIZE_K(64)>;
-		zephyr,memory-region = "DTCM";
-	};
-
-	itcm: memory@0 {
-		compatible = "zephyr,memory-region", "arm,itcm";
-		reg = <0x00000000 DT_SIZE_K(16)>;
-		zephyr,memory-region = "ITCM";
-	};
-
 	soc {
 		compatible = "st,stm32f723", "st,stm32f7", "simple-bus";
 
@@ -39,26 +20,6 @@
 			phys = <&usbphyc>;
 			maximum-speed = "high-speed";
 		};
-
-		sdmmc2: sdmmc@40011c00 {
-			compatible = "st,stm32-sdmmc";
-			reg = <0x40011c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>,
-				 <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
-			resets = <&rctl STM32_RESET(APB2, 7U)>;
-			interrupts = <103 0>;
-			status = "disabled";
-		};
-	};
-
-	vref: vref {
-		compatible = "st,stm32-vref";
-		vrefint-cal-addr = <0x1FF07A2A>;
-	};
-
-	die_temp: dietemp {
-		ts-cal1-addr = <0x1FF07A2C>;
-		ts-cal2-addr = <0x1FF07A2E>;
 	};
 };
 
diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f722xx b/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f722xx
new file mode 100644
index 00000000000..5b85551f939
--- /dev/null
+++ b/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f722xx
@@ -0,0 +1,15 @@
+# ST STM32F722XE Configuration options
+#
+# Copyright (c) 2023 Evan Perry Grove
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32F722XX
+
+config SOC
+	default "stm32f722xx"
+
+config NUM_IRQS
+	default 104
+
+endif # SOC_STM32F722XX
diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.soc b/soc/arm/st_stm32/stm32f7/Kconfig.soc
index 727ed908813..c83a9962a60 100644
--- a/soc/arm/st_stm32/stm32f7/Kconfig.soc
+++ b/soc/arm/st_stm32/stm32f7/Kconfig.soc
@@ -3,12 +3,16 @@
 # Copyright (c) 2018 Yurii Hamann
 # Copyright (c) 2022, Rtone.
 # Copyright (c) 2023, Rahul Arasikere.
+# Copyright (c) 2023 Evan Perry Grove
 # SPDX-License-Identifier: Apache-2.0
 
 choice
 	prompt "STM32F7x MCU Selection"
 	depends on SOC_SERIES_STM32F7X
 
+config SOC_STM32F722XX
+	bool "STM32F722XX"
+
 config SOC_STM32F723XX
 	bool "STM32F723XX"