xtensa: New asm layer to support SMP
SMP needs a new context switch primitive (to disentangle _swap() from the scheduler) and new interrupt entry behavior (to be able to take a global spinlock on behalf of legacy drivers). The existing code is very obtuse, and working with it led me down a long path of "this would be so much better if..." So this is a new context and entry framework, intended to replace the code that exists now, at least on SMP platforms. New features: * The new context switch primitive is xtensa_switch(), which takes a "new" context handle as an argument instead of getting it from the scheduler, returns an "old" context handle through a pointer (e.g. to save it to the old thread context), and restores the lock state(PS register) exactly as it is at entry instead of taking it as an argument. * The register spill code understands wrap-around register windows and can avoid spilling A4-A15 registers when they are unused by the interrupted function, saving as much as 48 bytes of stack space on the interrupted stacks. * The "spill register windows" routine is entirely different, using a different mechanism, and is MUCH FASTER (to the tune of almost 200 cycles). See notes in comments. * Even better, interrupt entry can be done via a clever "cross stack call" I worked up, meaning that the interrupted thread's registers do not need to be spilled at all until they are naturally pushed out by the interrupt handler or until we return from the interrupt into a different thread. This is a big efficiency win for tiny interrupts (e.g. timers), and a big latency win for all interrupts. * Interrupt entry is 100% symmetric with respect to medium/high interrupts, avoiding the problems seen with hooking high priority interrupts with the current code (e.g. ESP-32's watchdog driver). * Much smaller code size. No cut and paste assembly. No use of HAL calls. * Assumes "XEA2" interrupt architecture, the register window extension (i.e. no CALL0 ABI), and the "high priority interrupts" extension. Does not support the legacy processor variants for which we have no targets. The old code has some stuff in there to support this, but it seems bitrotten, untestable, and I'm all but certain it doesn't work. Note that this simply adds the primitives to the existing tree in a form where they can be unit tested. It does not replace the existing interrupt/exception handling or _Swap() implementation. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross
Anas Nashif
parent
8dca7ae587
commit
a34f884f23
6 changed files with 717 additions and 0 deletions
209
arch/xtensa/core/xtensa-asm2-util.S
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arch/xtensa/core/xtensa-asm2-util.S
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/*
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* Copyright (c) 2017, Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa-asm2-s.h>
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/*
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* xtensa_save_high_regs
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*
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* Call with CALL0, with A2/A3 available as scratch. Pushes the high
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* A4-A15 GPRs to the stack if needed (i.e. if those registers are not
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* part of wrapped-around frames higher up the call stack), returning
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* to the caller with the stack pointer HAVING BEEN MODIFIED to
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* contain them.
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*/
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.global xtensa_save_high_regs
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.align 4
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xtensa_save_high_regs:
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/* Generate a rotated (modulo NREGS/4 bits!) WINDOWSTART in A2
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* by duplicating the bits twice and shifting down by WINDOWBASE
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* bits. Now the LSB is the register quad at WINDOWBASE.
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*/
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rsr.WINDOWSTART a2
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slli a3, a2, (XCHAL_NUM_AREGS / 4)
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or a2, a2, a3
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rsr.WINDOWBASE a3
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ssr a3
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srl a2, a2
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mov a3, a1 /* Stash our original stack pointer */
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/* For the next three bits in WINDOWSTART (which correspond to
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* the A4-A7, A8-A11 and A12-A15 quads), if we find a one,
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* that means that the quad is owned by a wrapped-around call
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* in the registers, so we don't need to spill it or any
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* further registers from the GPRs and can skip to the end.
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*/
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bbsi a2, 1, _high_gpr_spill_done
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addi a1, a1, -16
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s32i a4, a1, 0
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s32i a5, a1, 4
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s32i a6, a1, 8
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s32i a7, a1, 12
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bbsi a2, 2, _high_gpr_spill_done
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addi a1, a1, -16
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s32i a8, a1, 0
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s32i a9, a1, 4
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s32i a10, a1, 8
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s32i a11, a1, 12
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bbsi a2, 3, _high_gpr_spill_done
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addi a1, a1, -16
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s32i a12, a1, 0
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s32i a13, a1, 4
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s32i a14, a1, 8
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s32i a15, a1, 12
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_high_gpr_spill_done:
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/* Push the original stack pointer so we know at restore
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* time how many registers were spilled, then return, leaving the
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* modified SP in A1.
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*/
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addi a1, a1, -4
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s32i a3, a1, 0
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ret
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/*
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* xtensa_restore_high_regs
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*
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* Does the inverse of xtensa_save_high_regs, taking a stack pointer
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* in A1 that resulted and restoring the A4-A15 state (and the stack
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* pointer) to the state they had at the earlier call. Call with
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* CALL0, leaving A2/A3 available as scratch.
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*/
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.global xtensa_restore_high_regs
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.align 4
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xtensa_restore_high_regs:
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/* pop our "original" stack pointer into a2, stash in a3 also */
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l32i a2, a1, 0
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addi a1, a1, 4
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mov a3, a2
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beq a1, a2, _high_restore_done
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addi a2, a2, -16
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l32i a4, a2, 0
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l32i a5, a2, 4
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l32i a6, a2, 8
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l32i a7, a2, 12
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beq a1, a2, _high_restore_done
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addi a2, a2, -16
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l32i a8, a2, 0
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l32i a9, a2, 4
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l32i a10, a2, 8
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l32i a11, a2, 12
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beq a1, a2, _high_restore_done
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addi a2, a2, -16
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l32i a12, a2, 0
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l32i a13, a2, 4
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l32i a14, a2, 8
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l32i a15, a2, 12
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_high_restore_done:
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mov a1, a3 /* Original stack */
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ret
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/*
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* _restore_context
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*
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* Arrive here via a jump. Enters into the restored context and does
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* not return. A1 should have a context pointer in it as received
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* from switch or an interrupt exit. Interrupts must be disabled,
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* and register windows should have been spilled.
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*
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* Note that exit from the restore is done with the RFI instruction,
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* using the EPCn/EPSn registers. Those will have been saved already
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* by any interrupt entry so they are save to use. Note that EPC1 and
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* RFE are NOT usable (they can't preserve PS). Per the ISA spec, all
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* RFI levels do the same thing and differ only in the special
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* registers used to hold PC/PS, but Qemu has been observed to behave
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* strangely when RFI doesn't "return" to a INTLEVEL strictly lower
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* than it started from. So pick level 6 (the highest that works on
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* Qemu, hardware doesn't care so it doesn't matter). In theory we
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* should test to be able to support hardware with less than 6 levels,
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* though...
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*/
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.global _restore_context
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_restore_context:
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call0 xtensa_restore_high_regs
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l32i a0, a1, BSA_PC_OFF
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wsr.EPC6 a0
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l32i a0, a1, BSA_PS_OFF
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wsr.EPS6 a0
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l32i a0, a1, BSA_SAR_OFF
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wsr.SAR a0
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#if XCHAL_HAVE_LOOPS
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l32i a0, a1, BSA_LBEG_OFF
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wsr.LBEG a0
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l32i a0, a1, BSA_LEND_OFF
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wsr.LEND a0
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l32i a0, a1, BSA_LCOUNT_OFF
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wsr.LCOUNT a0
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#endif
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rsync
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l32i a0, a1, BSA_A0_OFF
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l32i a2, a1, BSA_A2_OFF
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l32i a3, a1, BSA_A3_OFF
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addi a1, a1, BASE_SAVE_AREA_SIZE
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rfi 6
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/*
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* void xtensa_switch(void *new, void **old_return);
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*
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* Context switches into the prevoiusly-saved "new" handle, placing
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* the saved "old" handle into the address provided by old_return.
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*/
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.global xtensa_switch
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.align 4
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xtensa_switch:
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entry a1, 16
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SPILL_ALL_WINDOWS
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addi a1, a1, -BASE_SAVE_AREA_SIZE
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/* Stash our A0/2/3 and the shift/loop registers into the base
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* save area so they get restored as they are now. A2/A3
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* don't actually get used post-restore, but they need to be
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* stashed across the xtensa_save_high_regs call and this is a
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* convenient place.
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*/
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s32i a0, a1, BSA_A0_OFF
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s32i a2, a1, BSA_A2_OFF
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s32i a3, a1, BSA_A3_OFF
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ODD_REG_SAVE
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/* Stash our PS register contents and a "restore" PC. */
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rsr.PS a0
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s32i a0, a1, BSA_PS_OFF
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movi a0, _switch_restore_pc
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s32i a0, a1, BSA_PC_OFF
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/* Now the high registers */
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call0 xtensa_save_high_regs
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/* Restore the A3 argument we spilled earlier (via the base
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* save pointer pushed at the bottom of the stack) and set the
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* stack to the "new" context out of the A2 spill slot.
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*/
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l32i a2, a1, 0
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l32i a3, a2, BSA_A3_OFF
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s32i a1, a3, 0
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/* Switch stack pointer and restore. The jump to
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* _restore_context does not return as such, but we arrange
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* for the restored "next" address to be immediately after for
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* sanity.
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*/
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l32i a1, a2, BSA_A2_OFF
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j _restore_context
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_switch_restore_pc:
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retw
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