xtensa: Make high priority interrupts optional
Xtensa has a "high priority" class of interrupt levels which ignore the EXCM bit and can thus interrupt running exception handlers. These can't be used for C handlers in the general case[1] because C code needs to be able to throw window over/underflow exceptions, which are not reentrant. But the high priority interrupts might be useful to a carefully designed application, or to unit tests of low level architecture code. So make their generation optional with this kconfig option. [1] ESP-32 has a high priority interrupt for its watchdog, apparently. Which is sort of OK given that it never needs to return to the interrupted code. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
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2 changed files with 37 additions and 16 deletions
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@ -76,6 +76,23 @@ config IRQ_OFFLOAD_INTNUM
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Please note that in order for IRQ offload to work correctly the selected
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interrupt shall have its priority shall not exceed XCHAL_EXCM_LEVEL.
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config XTENSA_OMIT_HIGH_INTERRUPTS
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bool
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prompt "Skip generation of vectors for high priority interrupts"
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default n
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help
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Setting this to y causes the interrupt vectors for "high
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priority" Xtensa interrupts (those not masked by the EXCM bit
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in PS) to be left ungenerated, so they can be handled by
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application code instead. Note that high priority interrupts
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cannot safely be handled by C code anyway (they will interrupt
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register window exceptions, which cannot be made reentrant, so
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the code under the handler must not emit them), though some
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devices might still want to use built-in handling for things
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like watchdogs which do not need to return into interrupted
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code. Default is "n" for legacy compatibility. Consider
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changing to "y" in the future.
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config TOOLCHAIN_VARIANT
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string
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default RG-2016.4-linux
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@ -80,6 +80,16 @@
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#include <offsets_short.h>
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#include "xtensa_rtos.h"
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#define GEN_MED_INTERRUPT(l) \
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(XCHAL_NUM_INTLEVELS >= (l) && \
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XCHAL_DEBUGLEVEL != (l) && \
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XCHAL_EXCM_LEVEL >= (l))
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#define GEN_HIGH_INTERRUPT(l) \
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(XCHAL_NUM_INTLEVELS >= (l) && \
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XCHAL_DEBUGLEVEL != (l) && \
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(XCHAL_EXCM_LEVEL < (l) && !defined(CONFIG_XTENSA_OMIT_HIGH_INTERRUPTS)))
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/*
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* Defines used to access _xtos_interrupt_table.
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*/
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@ -1015,7 +1025,7 @@ _xt_lowint1:
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* repeated 5 times!!
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*/
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#if XCHAL_EXCM_LEVEL >= 2
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#if GEN_MED_INTERRUPT(2)
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.begin literal_prefix .Level2InterruptVector
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.section .Level2InterruptVector.text, "ax"
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@ -1088,7 +1098,7 @@ _xt_medint2_exit:
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#endif /* Level 2 */
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#if XCHAL_EXCM_LEVEL >= 3
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#if GEN_MED_INTERRUPT(3)
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.begin literal_prefix .Level3InterruptVector
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.section .Level3InterruptVector.text, "ax"
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@ -1161,12 +1171,7 @@ _xt_medint3_exit:
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#endif /* Level 3 */
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/* FIXME: For some reason, the HAL provided by the ESP32 port of FreeRTOS,
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* that Zephyr uses, defines XCHAL_EXCM_LEVEL to 3. That essentially
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* enables the other _Level4Vector routine, that doesn't work on ESP32.
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* This is tracked by: https://jira.zephyrproject.org/browse/ZEP-2570
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*/
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#if defined(CONFIG_SOC_ESP32) || (XCHAL_EXCM_LEVEL >= 4)
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#if GEN_MED_INTERRUPT(4)
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.begin literal_prefix .Level4InterruptVector
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.section .Level4InterruptVector.text, "ax"
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@ -1238,7 +1243,7 @@ _xt_medint4_exit:
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#endif /* Level 4 */
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#if XCHAL_EXCM_LEVEL >= 5
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#if GEN_MED_INTERRUPT(5)
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.begin literal_prefix .Level5InterruptVector
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.section .Level5InterruptVector.text, "ax"
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@ -1310,7 +1315,7 @@ _xt_medint5_exit:
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#endif /* Level 5 */
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#if XCHAL_EXCM_LEVEL >= 6
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#if GEN_MED_INTERRUPT(6)
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.begin literal_prefix .Level6InterruptVector
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.section .Level6InterruptVector.text, "ax"
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@ -1418,7 +1423,7 @@ _xt_medint6_exit:
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* Systems tools documentation: "Microprocessor Programmer's Guide".
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*/
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#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
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#if GEN_HIGH_INTERRUPT(2)
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.begin literal_prefix .Level2InterruptVector
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.section .Level2InterruptVector.text, "ax"
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@ -1455,7 +1460,7 @@ _xt_highint2:
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#endif /* Level 2 */
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#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
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#if GEN_HIGH_INTERRUPT(3)
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.begin literal_prefix .Level3InterruptVector
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.section .Level3InterruptVector.text, "ax"
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@ -1493,7 +1498,7 @@ _xt_highint3:
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#endif /* Level 3 */
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#if !defined(CONFIG_SOC_ESP32) && XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
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#if GEN_HIGH_INTERRUPT(4)
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.begin literal_prefix .Level4InterruptVector
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.section .Level4InterruptVector.text, "ax"
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@ -1531,8 +1536,7 @@ _xt_highint4:
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#endif /* Level 4 */
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#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
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#if GEN_HIGH_INTERRUPT(5)
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.begin literal_prefix .Level5InterruptVector
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.section .Level5InterruptVector.text, "ax"
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.global _Level5Vector
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@ -1571,7 +1575,7 @@ _xt_highint5:
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#endif /* Level 5 */
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#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
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#if GEN_HIGH_INTERRUPT(6)
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.begin literal_prefix .Level6InterruptVector
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.section .Level6InterruptVector.text, "ax"
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