treewide: rename Microsemi to Microchip
Do a treewide Microsemi to Microchip rename and update obsolete links in the board docs. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
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13 changed files with 20 additions and 22 deletions
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@ -519,7 +519,7 @@
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/dts/arm/silabs/efr32fg13* @yonsch
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/dts/arm/silabs/efr32fg13* @yonsch
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/dts/riscv/ @kgugala @pgielda
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/dts/riscv/ @kgugala @pgielda
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/dts/riscv/ite/ @ite
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/dts/riscv/ite/ @ite
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/dts/riscv/microsemi/microsemi-miv.dtsi @galak
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/dts/riscv/microchip/microchip-miv.dtsi @galak
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/dts/riscv/openisa/rv32m1* @dleach02
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/dts/riscv/openisa/rv32m1* @dleach02
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/dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda
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/dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda
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/dts/riscv/starfive/ @rajnesh-kanwal
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/dts/riscv/starfive/ @rajnesh-kanwal
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@ -1,5 +1,5 @@
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# SPDX-License-Identifier: Apache-2.0
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_M2GL025_MIV
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config BOARD_M2GL025_MIV
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bool "Microsemi M2GL025 IGLOO2 dev board with Mi-V CPU"
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bool "Microchip M2GL025 IGLOO2 dev board with Mi-V CPU"
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depends on SOC_RISCV32_MIV
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depends on SOC_RISCV32_MIV
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@ -1,15 +1,15 @@
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.. _m2gl025-miv:
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.. _m2gl025-miv:
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Microsemi M2GL025 Mi-V
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Microchip M2GL025 Mi-V
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######################
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######################
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Overview
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Overview
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********
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********
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The Microsemi M2GL025 board is an IGLOO2 FPGA based development board.
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The Microchip M2GL025 board is an IGLOO2 FPGA based development board.
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The Mi-V RISC-V soft CPU can be deployed on the MGL025 board.
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The Mi-V RISC-V soft CPU can be deployed on the MGL025 board.
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More information can be found on
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More information can be found on
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`Microsemi's website <https://www.microsemi.com/product-directory/embedded-processing/4406-cpus>`_.
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`Microchip's website <https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/mi-v>`_.
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Programming and debugging
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Programming and debugging
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*************************
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*************************
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@ -31,8 +31,8 @@ In order to upload the application to the device, you'll need OpenOCD and GDB
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with RISC-V support.
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with RISC-V support.
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You can get them as a part of SoftConsole SDK.
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You can get them as a part of SoftConsole SDK.
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Download and installation instructions can be found on
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Download and installation instructions can be found on
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`Microsemi's SoftConsole website
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`Microchip's SoftConsole website
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<https://www.microsemi.com/product-directory/design-tools/4879-softconsole>`_.
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<https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/soc-fpga/softconsole>`_.
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With the necessary tools installed, you can connect to the board using OpenOCD.
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With the necessary tools installed, you can connect to the board using OpenOCD.
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To establish an OpenOCD connection run:
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To establish an OpenOCD connection run:
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@ -6,7 +6,7 @@
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/dts-v1/;
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/dts-v1/;
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#include <microsemi/microsemi-miv.dtsi>
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#include <microchip/microchip-miv.dtsi>
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/ {
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/ {
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model = "SiFive HiFive 1";
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model = "SiFive HiFive 1";
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@ -1,5 +1,5 @@
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identifier: m2gl025_miv
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identifier: m2gl025_miv
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name: Microsemi M2GL025 with MiV target
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name: Microchip M2GL025 with MiV target
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type: mcu
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type: mcu
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arch: riscv32
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arch: riscv32
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toolchain:
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toolchain:
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@ -2,7 +2,7 @@
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# SPDX-License-Identifier: Apache-2.0
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MPFS_ICICLE
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config BOARD_MPFS_ICICLE
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bool "Microsemi PolarFire SoC ICICLE kit"
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bool "Microchip PolarFire SoC ICICLE kit"
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depends on SOC_MPFS
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depends on SOC_MPFS
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select 64BIT
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select 64BIT
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select SCHED_IPI_SUPPORTED
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select SCHED_IPI_SUPPORTED
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@ -6,7 +6,7 @@
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config UART_MIV
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config UART_MIV
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bool "Mi-V serial driver"
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bool "Mi-V serial driver"
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default y
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default y
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depends on DT_HAS_MICROSEMI_COREUART_ENABLED
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depends on DT_HAS_MICROCHIP_COREUART_ENABLED
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select SERIAL_HAS_DRIVER
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select SERIAL_HAS_DRIVER
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select SERIAL_SUPPORT_INTERRUPT
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select SERIAL_SUPPORT_INTERRUPT
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help
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help
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@ -4,7 +4,7 @@
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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#define DT_DRV_COMPAT microsemi_coreuart
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#define DT_DRV_COMPAT microchip_coreuart
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#include <zephyr/kernel.h>
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/arch/cpu.h>
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@ -3,7 +3,7 @@
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description: SiFive UART
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description: SiFive UART
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compatible: "microsemi,coreuart"
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compatible: "microchip,coreuart"
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include: uart-controller.yaml
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include: uart-controller.yaml
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@ -375,7 +375,6 @@ microbit Micro:bit Educational Foundation
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microchip Microchip Technology Inc.
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microchip Microchip Technology Inc.
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microcrystal Micro Crystal AG
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microcrystal Micro Crystal AG
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micron Micron Technology Inc.
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micron Micron Technology Inc.
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microsemi Microchip Technology Inc. (formerly Microsemi Corporation)
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microsoft Microsoft Corporation
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microsoft Microsoft Corporation
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microsys MicroSys Electronics GmbH
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microsys MicroSys Electronics GmbH
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mikroe MikroElektronika d.o.o.
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mikroe MikroElektronika d.o.o.
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@ -392,7 +391,6 @@ mpl MPL AG
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mps Monolithic Power Systems Inc.
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mps Monolithic Power Systems Inc.
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mqmaker mqmaker Inc.
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mqmaker mqmaker Inc.
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mrvl Marvell Technology Group Ltd.
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mrvl Marvell Technology Group Ltd.
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mscc Microsemi Corporation
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msi Micro-Star International Co. Ltd.
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msi Micro-Star International Co. Ltd.
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mstar MStar Semiconductor, Inc. (acquired by MediaTek Inc.)
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mstar MStar Semiconductor, Inc. (acquired by MediaTek Inc.)
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mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
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mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
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@ -13,7 +13,7 @@
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#size-cells = <0>;
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#size-cells = <0>;
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cpu@0 {
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cpu@0 {
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clock-frequency = <0>;
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clock-frequency = <0>;
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compatible = "microsemi,miv", "riscv";
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compatible = "microchip,miv", "riscv";
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device_type = "cpu";
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device_type = "cpu";
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reg = <0>;
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reg = <0>;
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riscv,isa = "rv32imac";
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riscv,isa = "rv32imac";
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soc {
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soc {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <1>;
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compatible = "microsemi,miv-soc", "simple-bus";
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compatible = "microchip,miv-soc", "simple-bus";
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ranges;
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ranges;
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flash0: flash@80000000 {
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flash0: flash@80000000 {
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};
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};
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uart0: uart@70001000 {
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uart0: uart@70001000 {
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compatible = "microsemi,coreuart";
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compatible = "microchip,coreuart";
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reg = <0x70001000 0x1000>;
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reg = <0x70001000 0x1000>;
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status = "disabled";
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status = "disabled";
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current-speed = <0>;
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current-speed = <0>;
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# SPDX-License-Identifier: Apache-2.0
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RISCV32_MIV
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config SOC_SERIES_RISCV32_MIV
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bool "Microsemi Mi-V implementation"
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bool "Microchip Mi-V implementation"
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select RISCV
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select RISCV
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select SOC_FAMILY_RISCV_PRIVILEGE
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select SOC_FAMILY_RISCV_PRIVILEGE
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help
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help
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Enable support for Microsemi Mi-V
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Enable support for Microchip Mi-V
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@ -4,11 +4,11 @@
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# SPDX-License-Identifier: Apache-2.0
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# SPDX-License-Identifier: Apache-2.0
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choice
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choice
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prompt "Microsemi Mi-V system implementation"
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prompt "Microchip Mi-V system implementation"
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depends on SOC_SERIES_RISCV32_MIV
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depends on SOC_SERIES_RISCV32_MIV
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config SOC_RISCV32_MIV
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config SOC_RISCV32_MIV
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bool "Microsemi Mi-V system implementation"
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bool "Microchip Mi-V system implementation"
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select ATOMIC_OPERATIONS_C
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select ATOMIC_OPERATIONS_C
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select INCLUDE_RESET_VECTOR
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select INCLUDE_RESET_VECTOR
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select RISCV_ISA_RV32I
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select RISCV_ISA_RV32I
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