diff --git a/CODEOWNERS b/CODEOWNERS index bc22b561ea6..9a4d54f6235 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -519,7 +519,7 @@ /dts/arm/silabs/efr32fg13* @yonsch /dts/riscv/ @kgugala @pgielda /dts/riscv/ite/ @ite -/dts/riscv/microsemi/microsemi-miv.dtsi @galak +/dts/riscv/microchip/microchip-miv.dtsi @galak /dts/riscv/openisa/rv32m1* @dleach02 /dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda /dts/riscv/starfive/ @rajnesh-kanwal diff --git a/boards/riscv/m2gl025_miv/Kconfig.board b/boards/riscv/m2gl025_miv/Kconfig.board index 9154176ece6..51c2f9d8de3 100644 --- a/boards/riscv/m2gl025_miv/Kconfig.board +++ b/boards/riscv/m2gl025_miv/Kconfig.board @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_M2GL025_MIV - bool "Microsemi M2GL025 IGLOO2 dev board with Mi-V CPU" + bool "Microchip M2GL025 IGLOO2 dev board with Mi-V CPU" depends on SOC_RISCV32_MIV diff --git a/boards/riscv/m2gl025_miv/doc/index.rst b/boards/riscv/m2gl025_miv/doc/index.rst index 857b2871497..cc9a24c866b 100644 --- a/boards/riscv/m2gl025_miv/doc/index.rst +++ b/boards/riscv/m2gl025_miv/doc/index.rst @@ -1,15 +1,15 @@ .. _m2gl025-miv: -Microsemi M2GL025 Mi-V +Microchip M2GL025 Mi-V ###################### Overview ******** -The Microsemi M2GL025 board is an IGLOO2 FPGA based development board. +The Microchip M2GL025 board is an IGLOO2 FPGA based development board. The Mi-V RISC-V soft CPU can be deployed on the MGL025 board. More information can be found on -`Microsemi's website `_. +`Microchip's website `_. Programming and debugging ************************* @@ -31,8 +31,8 @@ In order to upload the application to the device, you'll need OpenOCD and GDB with RISC-V support. You can get them as a part of SoftConsole SDK. Download and installation instructions can be found on -`Microsemi's SoftConsole website -`_. +`Microchip's SoftConsole website +`_. With the necessary tools installed, you can connect to the board using OpenOCD. To establish an OpenOCD connection run: diff --git a/boards/riscv/m2gl025_miv/m2gl025_miv.dts b/boards/riscv/m2gl025_miv/m2gl025_miv.dts index cb072af6e93..70de61ec907 100644 --- a/boards/riscv/m2gl025_miv/m2gl025_miv.dts +++ b/boards/riscv/m2gl025_miv/m2gl025_miv.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include / { model = "SiFive HiFive 1"; diff --git a/boards/riscv/m2gl025_miv/m2gl025_miv.yaml b/boards/riscv/m2gl025_miv/m2gl025_miv.yaml index 883af700d06..283269bb32e 100644 --- a/boards/riscv/m2gl025_miv/m2gl025_miv.yaml +++ b/boards/riscv/m2gl025_miv/m2gl025_miv.yaml @@ -1,5 +1,5 @@ identifier: m2gl025_miv -name: Microsemi M2GL025 with MiV target +name: Microchip M2GL025 with MiV target type: mcu arch: riscv32 toolchain: diff --git a/boards/riscv/mpfs_icicle/Kconfig.board b/boards/riscv/mpfs_icicle/Kconfig.board index ce35042e906..297f4ce4bc7 100644 --- a/boards/riscv/mpfs_icicle/Kconfig.board +++ b/boards/riscv/mpfs_icicle/Kconfig.board @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_MPFS_ICICLE - bool "Microsemi PolarFire SoC ICICLE kit" + bool "Microchip PolarFire SoC ICICLE kit" depends on SOC_MPFS select 64BIT select SCHED_IPI_SUPPORTED diff --git a/drivers/serial/Kconfig.miv b/drivers/serial/Kconfig.miv index ebf7319f8cf..3ac7ef3c2a0 100644 --- a/drivers/serial/Kconfig.miv +++ b/drivers/serial/Kconfig.miv @@ -6,7 +6,7 @@ config UART_MIV bool "Mi-V serial driver" default y - depends on DT_HAS_MICROSEMI_COREUART_ENABLED + depends on DT_HAS_MICROCHIP_COREUART_ENABLED select SERIAL_HAS_DRIVER select SERIAL_SUPPORT_INTERRUPT help diff --git a/drivers/serial/uart_miv.c b/drivers/serial/uart_miv.c index 339b521e71e..24dbf3af370 100644 --- a/drivers/serial/uart_miv.c +++ b/drivers/serial/uart_miv.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT microsemi_coreuart +#define DT_DRV_COMPAT microchip_coreuart #include #include diff --git a/dts/bindings/serial/microsemi,coreuart.yaml b/dts/bindings/serial/microchip,coreuart.yaml similarity index 83% rename from dts/bindings/serial/microsemi,coreuart.yaml rename to dts/bindings/serial/microchip,coreuart.yaml index e5764a21a19..c9776e5b9d4 100644 --- a/dts/bindings/serial/microsemi,coreuart.yaml +++ b/dts/bindings/serial/microchip,coreuart.yaml @@ -3,7 +3,7 @@ description: SiFive UART -compatible: "microsemi,coreuart" +compatible: "microchip,coreuart" include: uart-controller.yaml diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index 18fe3b87759..dd01c5b57a6 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -375,7 +375,6 @@ microbit Micro:bit Educational Foundation microchip Microchip Technology Inc. microcrystal Micro Crystal AG micron Micron Technology Inc. -microsemi Microchip Technology Inc. (formerly Microsemi Corporation) microsoft Microsoft Corporation microsys MicroSys Electronics GmbH mikroe MikroElektronika d.o.o. @@ -392,7 +391,6 @@ mpl MPL AG mps Monolithic Power Systems Inc. mqmaker mqmaker Inc. mrvl Marvell Technology Group Ltd. -mscc Microsemi Corporation msi Micro-Star International Co. Ltd. mstar MStar Semiconductor, Inc. (acquired by MediaTek Inc.) mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) diff --git a/dts/riscv/microsemi/microsemi-miv.dtsi b/dts/riscv/microchip/microchip-miv.dtsi similarity index 91% rename from dts/riscv/microsemi/microsemi-miv.dtsi rename to dts/riscv/microchip/microchip-miv.dtsi index 82d6e80780d..5ef8b3a4931 100644 --- a/dts/riscv/microsemi/microsemi-miv.dtsi +++ b/dts/riscv/microchip/microchip-miv.dtsi @@ -13,7 +13,7 @@ #size-cells = <0>; cpu@0 { clock-frequency = <0>; - compatible = "microsemi,miv", "riscv"; + compatible = "microchip,miv", "riscv"; device_type = "cpu"; reg = <0>; riscv,isa = "rv32imac"; @@ -29,7 +29,7 @@ soc { #address-cells = <1>; #size-cells = <1>; - compatible = "microsemi,miv-soc", "simple-bus"; + compatible = "microchip,miv-soc", "simple-bus"; ranges; flash0: flash@80000000 { @@ -63,7 +63,7 @@ }; uart0: uart@70001000 { - compatible = "microsemi,coreuart"; + compatible = "microchip,coreuart"; reg = <0x70001000 0x1000>; status = "disabled"; current-speed = <0>; diff --git a/soc/riscv/riscv-privilege/miv/Kconfig.series b/soc/riscv/riscv-privilege/miv/Kconfig.series index 6e10f7f62f0..dc69e90517d 100644 --- a/soc/riscv/riscv-privilege/miv/Kconfig.series +++ b/soc/riscv/riscv-privilege/miv/Kconfig.series @@ -4,8 +4,8 @@ # SPDX-License-Identifier: Apache-2.0 config SOC_SERIES_RISCV32_MIV - bool "Microsemi Mi-V implementation" + bool "Microchip Mi-V implementation" select RISCV select SOC_FAMILY_RISCV_PRIVILEGE help - Enable support for Microsemi Mi-V + Enable support for Microchip Mi-V diff --git a/soc/riscv/riscv-privilege/miv/Kconfig.soc b/soc/riscv/riscv-privilege/miv/Kconfig.soc index 2c7a1e24876..88f5a9faf42 100644 --- a/soc/riscv/riscv-privilege/miv/Kconfig.soc +++ b/soc/riscv/riscv-privilege/miv/Kconfig.soc @@ -4,11 +4,11 @@ # SPDX-License-Identifier: Apache-2.0 choice - prompt "Microsemi Mi-V system implementation" + prompt "Microchip Mi-V system implementation" depends on SOC_SERIES_RISCV32_MIV config SOC_RISCV32_MIV - bool "Microsemi Mi-V system implementation" + bool "Microchip Mi-V system implementation" select ATOMIC_OPERATIONS_C select INCLUDE_RESET_VECTOR select RISCV_ISA_RV32I