From 9f76adbfa846b7f4b5711644c2c43b69d287220c Mon Sep 17 00:00:00 2001 From: Attie Grande Date: Sun, 26 Nov 2023 15:37:34 +0000 Subject: [PATCH] soc: atmel_sam0: Setup clocks for USB on SAML21 parts GCLK Gen 2 was dedicated to USB, but never setup... this patch configures it for 48 MHz, derrived from DFLL. Signed-off-by: Attie Grande --- soc/arm/atmel_sam0/common/soc_saml2x.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/soc/arm/atmel_sam0/common/soc_saml2x.c b/soc/arm/atmel_sam0/common/soc_saml2x.c index c4c1a659dd6..6f29f9c525d 100644 --- a/soc/arm/atmel_sam0/common/soc_saml2x.c +++ b/soc/arm/atmel_sam0/common/soc_saml2x.c @@ -215,6 +215,18 @@ static inline void gclk_main_configure(void) GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_DFLL48M_Val; } +#if !CONFIG_USB_DC_SAM0 +#define gclk_usb_configure() +#else +static inline void gclk_usb_configure(void) +{ + GCLK->GENCTRL[2].reg = 0 + | GCLK_GENCTRL_SRC_DFLL48M + | GCLK_GENCTRL_DIV(1) + | GCLK_GENCTRL_GENEN; +} +#endif + #if !CONFIG_ADC_SAM0 #define gclk_adc_configure() #else @@ -255,5 +267,6 @@ void z_arm_platform_init(void) flash_waitstates_init(); pm_init(); gclk_main_configure(); + gclk_usb_configure(); gclk_adc_configure(); }