michaelh/zephyr
1
0
Fork 0
Code Releases Activity

stm32: clock_control: fix APB2 peripheral clock control on stm32g0

Browse source 
The STM32G0 series of MCUs only has one APB, but two reset and clock
enable registers. Fix enabling/disabling the clock and getting the rate
for peripherals in the second register.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
This commit is contained in:
Filip Brozovic 2019-10-07 08:22:31 +02:00 • committed by Carles Cufí
commit 9e92babca2
1 changed files with 11 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

15
drivers/clock_control/clock_stm32_ll_common.c
View file

@ -111,11 +111,11 @@ static inline int stm32_clock_control_on(struct device *dev,
break; break;
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X || #endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X ||
CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */ CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X) #if !defined(CONFIG_SOC_SERIES_STM32F0X)
case STM32_CLOCK_BUS_APB2: case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_EnableClock(pclken->enr); LL_APB2_GRP1_EnableClock(pclken->enr);
break; break;
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */ #endif /* CONFIG_SOC_SERIES_STM32F0X */
#if defined (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X) #if defined (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X)
case STM32_CLOCK_BUS_IOP: case STM32_CLOCK_BUS_IOP:
LL_IOP_GRP1_EnableClock(pclken->enr); LL_IOP_GRP1_EnableClock(pclken->enr);
@ -162,11 +162,11 @@ static inline int stm32_clock_control_off(struct device *dev,
break; break;
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X || #endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X ||
CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */ CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X) #if !defined(CONFIG_SOC_SERIES_STM32F0X)
case STM32_CLOCK_BUS_APB2: case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_DisableClock(pclken->enr); LL_APB2_GRP1_DisableClock(pclken->enr);
break; break;
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */ #endif /* CONFIG_SOC_SERIES_STM32F0X */
#ifdef CONFIG_SOC_SERIES_STM32L0X #ifdef CONFIG_SOC_SERIES_STM32L0X
case STM32_CLOCK_BUS_IOP: case STM32_CLOCK_BUS_IOP:
LL_IOP_GRP1_DisableClock(pclken->enr); LL_IOP_GRP1_DisableClock(pclken->enr);
@ -216,6 +216,13 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock,
defined(CONFIG_SOC_SERIES_STM32G4X) defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_APB1_2: case STM32_CLOCK_BUS_APB1_2:
#endif #endif
#if defined(CONFIG_SOC_SERIES_STM32G0X)
case STM32_CLOCK_BUS_APB2:
/*
* STM32G0x only has one APB, but two reset/clock enable
* registers for peripherals, so return the APB1 clock rate here
*/
#endif /* CONFIG_SOC_SERIES_STM32G0X */
*rate = apb1_clock; *rate = apb1_clock;
break; break;
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X) #if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)