From 9e92babca27926465e96a53d2e5085ad0ad0cd3a Mon Sep 17 00:00:00 2001 From: Filip Brozovic Date: Mon, 7 Oct 2019 08:22:31 +0200 Subject: [PATCH] stm32: clock_control: fix APB2 peripheral clock control on stm32g0 The STM32G0 series of MCUs only has one APB, but two reset and clock enable registers. Fix enabling/disabling the clock and getting the rate for peripherals in the second register. Signed-off-by: Filip Brozovic --- drivers/clock_control/clock_stm32_ll_common.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c index 2c7693b5854..09bae73bf3e 100644 --- a/drivers/clock_control/clock_stm32_ll_common.c +++ b/drivers/clock_control/clock_stm32_ll_common.c @@ -111,11 +111,11 @@ static inline int stm32_clock_control_on(struct device *dev, break; #endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X || CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */ -#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X) +#if !defined(CONFIG_SOC_SERIES_STM32F0X) case STM32_CLOCK_BUS_APB2: LL_APB2_GRP1_EnableClock(pclken->enr); break; -#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */ +#endif /* CONFIG_SOC_SERIES_STM32F0X */ #if defined (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X) case STM32_CLOCK_BUS_IOP: LL_IOP_GRP1_EnableClock(pclken->enr); @@ -162,11 +162,11 @@ static inline int stm32_clock_control_off(struct device *dev, break; #endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X || CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */ -#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X) +#if !defined(CONFIG_SOC_SERIES_STM32F0X) case STM32_CLOCK_BUS_APB2: LL_APB2_GRP1_DisableClock(pclken->enr); break; -#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */ +#endif /* CONFIG_SOC_SERIES_STM32F0X */ #ifdef CONFIG_SOC_SERIES_STM32L0X case STM32_CLOCK_BUS_IOP: LL_IOP_GRP1_DisableClock(pclken->enr); @@ -216,6 +216,13 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock, defined(CONFIG_SOC_SERIES_STM32G4X) case STM32_CLOCK_BUS_APB1_2: #endif +#if defined(CONFIG_SOC_SERIES_STM32G0X) + case STM32_CLOCK_BUS_APB2: + /* + * STM32G0x only has one APB, but two reset/clock enable + * registers for peripherals, so return the APB1 clock rate here + */ +#endif /* CONFIG_SOC_SERIES_STM32G0X */ *rate = apb1_clock; break; #if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)