From 9df99945722eea99d29872d5e498a4edd89fe50d Mon Sep 17 00:00:00 2001 From: Andrew Boie Date: Tue, 10 Sep 2019 00:41:08 -0700 Subject: [PATCH] x86: fix XIP SOC support and defaults XIP support in x86 was something of a mess. This patch does the following: - Generic ia32 SOC no longer defines a "flash" region as generic X86 devices don't have a microcontroller- like concept of flash. The same has been done for apollo_lake. - Generic ia32 and apollo_lake SOCs starts memory at 1MB. - Generic ia32 SOC may optionally have CONFIG_XIP enabled. The board definition must provide a flash region definition that gets exposed as DT_PHYS_LOAD_ADDR. - Fixed definitions for RAM/ROM source addresses in ia32's linker.ld when XIP is turned off. - Support for enabling XIP on apollo_lake SOC removed, there's no use-case. - acrn and gpmrb boards have flash and XIP related definitions removed. - qemu_x86 has a fake flash region added, immediately after system RAM, for use when XIP is enabled. This used to be in the ia32 SOC. However, the default for qemu_x86 is to now have XIP disabled. - Fixed tests/kernel/xip to run by default on boards that enable XIP by default, plus an additional test to exercise XIP on qemu_x86 (which supports it but has XIP switched off by default) The overall effect of this patch is to: - Remove XIP configuration for SOC/boards where it does not make any sense to have it - Support testing XIP on qemu_x86 via tests/kernel/xip, but leave it off by default for other tests, to ensure it doesn't bit-rot and that the system works in both scenarios. - XIP remains an available feature for boards that need it. Fixes: #18956 Signed-off-by: Andrew Boie --- boards/x86/acrn/acrn.dts | 10 ---------- boards/x86/acrn/acrn.yaml | 2 +- boards/x86/acrn/acrn_defconfig | 1 - boards/x86/gpmrb/gpmrb.dts | 2 -- boards/x86/qemu_x86/Kconfig.board | 6 ------ boards/x86/qemu_x86/qemu_x86.dts | 7 ++++++- boards/x86/qemu_x86/qemu_x86_coverage_defconfig | 1 - boards/x86/up_squared/up_squared.dts | 2 -- dts/x86/apollo_lake.dtsi | 9 ++------- dts/x86/ia32.dtsi | 10 ++-------- soc/x86/apollo_lake/linker.ld | 17 +++-------------- soc/x86/ia32/linker.ld | 15 +++++++++------ tests/kernel/xip/prj.conf | 1 - tests/kernel/xip/testcase.yaml | 11 +++++++++-- 14 files changed, 32 insertions(+), 62 deletions(-) diff --git a/boards/x86/acrn/acrn.dts b/boards/x86/acrn/acrn.dts index 440959da2e1..671ad6b9489 100644 --- a/boards/x86/acrn/acrn.dts +++ b/boards/x86/acrn/acrn.dts @@ -8,7 +8,6 @@ #include -#define DT_FLASH_SIZE DT_SIZE_K(8192) #define DT_SRAM_SIZE DT_SIZE_K(8192) #include @@ -24,7 +23,6 @@ chosen { zephyr,sram = &sram0; - zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; }; @@ -39,11 +37,3 @@ status = "okay"; current-speed = <115200>; }; - -&flash0 { - reg = <0x100000 DT_FLASH_SIZE>; -}; - -&sram0 { - reg = <0x400000 DT_SRAM_SIZE>; -}; diff --git a/boards/x86/acrn/acrn.yaml b/boards/x86/acrn/acrn.yaml index 98b70b6b1f8..b48fe1228d1 100644 --- a/boards/x86/acrn/acrn.yaml +++ b/boards/x86/acrn/acrn.yaml @@ -5,4 +5,4 @@ arch: x86 toolchain: - zephyr ram: 8192 -flash: 8192 + diff --git a/boards/x86/acrn/acrn_defconfig b/boards/x86/acrn/acrn_defconfig index 427ce8b09f5..132f3965173 100644 --- a/boards/x86/acrn/acrn_defconfig +++ b/boards/x86/acrn/acrn_defconfig @@ -10,6 +10,5 @@ CONFIG_SERIAL=y CONFIG_UART_NS16550=y CONFIG_UART_CONSOLE=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 -CONFIG_XIP=n CONFIG_BUILD_OUTPUT_BIN=y CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n diff --git a/boards/x86/gpmrb/gpmrb.dts b/boards/x86/gpmrb/gpmrb.dts index a28c908fca3..433bafa78fc 100644 --- a/boards/x86/gpmrb/gpmrb.dts +++ b/boards/x86/gpmrb/gpmrb.dts @@ -8,7 +8,6 @@ #include -#define DT_FLASH_SIZE DT_SIZE_K(8912) #define DT_SRAM_SIZE DT_SIZE_M(2048) #include @@ -19,7 +18,6 @@ chosen { zephyr,sram = &sram0; - zephyr,flash = &flash0; zephyr,console = &uart2; zephyr,shell-uart = &uart2; zephyr,bt-uart = &uart1; diff --git a/boards/x86/qemu_x86/Kconfig.board b/boards/x86/qemu_x86/Kconfig.board index 0ac4e6d0368..3893e625755 100644 --- a/boards/x86/qemu_x86/Kconfig.board +++ b/boards/x86/qemu_x86/Kconfig.board @@ -1,9 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 -# -# The QEMU targets themselves are not XIP, everything is actually RAM, but we -# pretend the first 4 megabytes are a memory-mapped flash region. This is done -# to ensure that the XIP data copying infrastructure doesn't bit-rot on -# x86. config BOARD_QEMU_X86 bool "QEMU x86" @@ -12,4 +7,3 @@ config BOARD_QEMU_X86 select HAS_DTS_ETHERNET select CPU_HAS_FPU select HAS_COVERAGE_SUPPORT - select XIP diff --git a/boards/x86/qemu_x86/qemu_x86.dts b/boards/x86/qemu_x86/qemu_x86.dts index 731db7a3425..6eda4fc46ee 100644 --- a/boards/x86/qemu_x86/qemu_x86.dts +++ b/boards/x86/qemu_x86/qemu_x86.dts @@ -4,8 +4,8 @@ #include -#define DT_FLASH_SIZE DT_SIZE_K(4096) #define DT_SRAM_SIZE DT_SIZE_K(4096) +#define DT_FLASH_SIZE DT_SIZE_K(4096) #include @@ -13,6 +13,11 @@ model = "QEMU X86"; compatible = "intel,ia32"; + flash0: flash@500000 { + compatible = "soc-nv-flash"; + reg = <0x00500000 DT_FLASH_SIZE>; + }; + aliases { uart-0 = &uart0; uart-1 = &uart1; diff --git a/boards/x86/qemu_x86/qemu_x86_coverage_defconfig b/boards/x86/qemu_x86/qemu_x86_coverage_defconfig index 8b91763da45..565342117a5 100644 --- a/boards/x86/qemu_x86/qemu_x86_coverage_defconfig +++ b/boards/x86/qemu_x86/qemu_x86_coverage_defconfig @@ -14,7 +14,6 @@ CONFIG_UART_NS16550=y CONFIG_UART_CONSOLE=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_XIP=y CONFIG_X86_MMU=y CONFIG_X86_MMU_PAGE_POOL_PAGES=15 CONFIG_DEBUG_INFO=y diff --git a/boards/x86/up_squared/up_squared.dts b/boards/x86/up_squared/up_squared.dts index 0fd3789f5c2..17399864430 100644 --- a/boards/x86/up_squared/up_squared.dts +++ b/boards/x86/up_squared/up_squared.dts @@ -8,7 +8,6 @@ #include -#define DT_FLASH_SIZE DT_SIZE_K(8912) #define DT_SRAM_SIZE DT_SIZE_M(2048) #include @@ -19,7 +18,6 @@ chosen { zephyr,sram = &sram0; - zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,bt-uart = &uart1; diff --git a/dts/x86/apollo_lake.dtsi b/dts/x86/apollo_lake.dtsi index 6f066a7038e..ca4364a4c58 100644 --- a/dts/x86/apollo_lake.dtsi +++ b/dts/x86/apollo_lake.dtsi @@ -22,15 +22,10 @@ }; - flash0: flash@100000{ - compatible = "soc-nv-flash"; - reg = <0x00100000 DT_FLASH_SIZE>; - }; - - sram0: memory@400000 { + sram0: memory@100000 { device_type = "memory"; compatible = "mmio-sram"; - reg = <0x00400000 DT_SRAM_SIZE>; + reg = <0x00100000 DT_SRAM_SIZE>; }; intc: ioapic@fec00000 { diff --git a/dts/x86/ia32.dtsi b/dts/x86/ia32.dtsi index 3b203fdc7b0..4e6163845ee 100644 --- a/dts/x86/ia32.dtsi +++ b/dts/x86/ia32.dtsi @@ -27,16 +27,10 @@ #interrupt-cells = <3>; }; - - flash0: flash@100000 { - compatible = "soc-nv-flash"; - reg = <0x00100000 DT_FLASH_SIZE>; - }; - - sram0: memory@500000 { + sram0: memory@100000 { device_type = "memory"; compatible = "mmio-sram"; - reg = <0x00500000 DT_SRAM_SIZE>; + reg = <0x00100000 DT_SRAM_SIZE>; }; soc { diff --git a/soc/x86/apollo_lake/linker.ld b/soc/x86/apollo_lake/linker.ld index a5db250de47..6a10c7dd8d2 100644 --- a/soc/x86/apollo_lake/linker.ld +++ b/soc/x86/apollo_lake/linker.ld @@ -6,24 +6,13 @@ #include #include -/* physical address where the kernel is loaded */ -#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR -/* physical address of RAM */ -#ifdef CONFIG_XIP - #define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR -#else /* !CONFIG_XIP */ - #define PHYS_RAM_ADDR PHYS_LOAD_ADDR -#endif /* CONFIG_XIP */ +#define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR +#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR MEMORY { -#ifdef CONFIG_XIP - ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K - RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K -#else /* !CONFIG_XIP */ - RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_RAM_SIZE*1K -#endif /* CONFIG_XIP */ + RAM (wx) : ORIGIN = DT_PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K /* * It doesn't matter where this region goes as it is stripped from the diff --git a/soc/x86/ia32/linker.ld b/soc/x86/ia32/linker.ld index 218f61fd588..7551dbe459c 100644 --- a/soc/x86/ia32/linker.ld +++ b/soc/x86/ia32/linker.ld @@ -9,28 +9,31 @@ * @brief Linker command/script file * * This is the linker script for both standard images and XIP images. + * + * If XIP is turned on, board-level DTS must specify a flash region + * that doesn't overlap with sram0, so that DT_PHYS_LOAD_ADDR is set. */ #include #include /* physical address where the kernel is loaded */ -#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR - /* physical address of RAM */ #ifdef CONFIG_XIP - #define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR + #define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR + #define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR #else /* !CONFIG_XIP */ - #define PHYS_RAM_ADDR PHYS_LOAD_ADDR + #define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR + #define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR #endif /* CONFIG_XIP */ MEMORY { #ifdef CONFIG_XIP ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K - RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K + RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K #else /* !CONFIG_XIP */ - RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_RAM_SIZE*1K + RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K #endif /* CONFIG_XIP */ /* diff --git a/tests/kernel/xip/prj.conf b/tests/kernel/xip/prj.conf index 6e7e0d6ded9..9467c292689 100644 --- a/tests/kernel/xip/prj.conf +++ b/tests/kernel/xip/prj.conf @@ -1,2 +1 @@ -CONFIG_XIP=y CONFIG_ZTEST=y diff --git a/tests/kernel/xip/testcase.yaml b/tests/kernel/xip/testcase.yaml index ab5966c7629..ecc65d2e59e 100644 --- a/tests/kernel/xip/testcase.yaml +++ b/tests/kernel/xip/testcase.yaml @@ -1,5 +1,12 @@ tests: arch.common.xip: - arch_exclude: xtensa - platform_exclude: cc3220sf_launchxl minnowboard + filter: CONFIG_XIP + tags: xip + + # Platforms where XIP is supported but not on by default (rare, typically + # emulator targets, to show that XIP is working for a particular arch) + arch.common.xip.nondefault: + platform_whitelist: qemu_x86 qemu_x86_coverage + extra_configs: + - CONFIG_XIP=y tags: xip