From 9de3d6bf643455493dad32eda0c496cb97ee221a Mon Sep 17 00:00:00 2001 From: Henrik Lindblom Date: Tue, 15 Apr 2025 11:20:11 +0300 Subject: [PATCH] soc: stm32: use cache peripheral driver Use the Zephyr cache API in soc initialization code instead of calling the HAL directly. The change does not modify the pre-existing cache settings, just changes the path they are enabled. Signed-off-by: Henrik Lindblom --- soc/st/stm32/Kconfig.defconfig | 3 +++ soc/st/stm32/stm32h5x/Kconfig.defconfig | 13 ++++++++++++ soc/st/stm32/stm32h5x/soc.c | 6 ++---- soc/st/stm32/stm32l5x/Kconfig.defconfig | 10 +++++++++ soc/st/stm32/stm32l5x/soc.c | 7 ++---- soc/st/stm32/stm32u5x/Kconfig.defconfig | 13 ++++++++++++ soc/st/stm32/stm32u5x/power.c | 25 +++------------------- soc/st/stm32/stm32u5x/soc.c | 6 ++---- soc/st/stm32/stm32wbax/Kconfig.defconfig | 10 +++++++++ soc/st/stm32/stm32wbax/power.c | 27 ++++-------------------- soc/st/stm32/stm32wbax/soc.c | 6 ++---- 11 files changed, 64 insertions(+), 62 deletions(-) diff --git a/soc/st/stm32/Kconfig.defconfig b/soc/st/stm32/Kconfig.defconfig index b34e0c775be..1cf916d1611 100644 --- a/soc/st/stm32/Kconfig.defconfig +++ b/soc/st/stm32/Kconfig.defconfig @@ -11,6 +11,9 @@ if SOC_FAMILY_STM32 # can override the defaults given here rsource "*/Kconfig.defconfig" +config CACHE_STM32 + default y if EXTERNAL_CACHE + config CLOCK_CONTROL default y diff --git a/soc/st/stm32/stm32h5x/Kconfig.defconfig b/soc/st/stm32/stm32h5x/Kconfig.defconfig index f8167440f33..d3eb43e4286 100644 --- a/soc/st/stm32/stm32h5x/Kconfig.defconfig +++ b/soc/st/stm32/stm32h5x/Kconfig.defconfig @@ -7,6 +7,19 @@ if SOC_SERIES_STM32H5X rsource "Kconfig.defconfig.stm32h5*" +config ICACHE + default y + +config DCACHE + default y if !SOC_STM32H503XX + +config CACHE_MANAGEMENT + default y + +choice CACHE_TYPE + default EXTERNAL_CACHE +endchoice + config ROM_START_OFFSET default 0x400 if BOOTLOADER_MCUBOOT diff --git a/soc/st/stm32/stm32h5x/soc.c b/soc/st/stm32/stm32h5x/soc.c index c4735c78c79..5ae4618b707 100644 --- a/soc/st/stm32/stm32h5x/soc.c +++ b/soc/st/stm32/stm32h5x/soc.c @@ -11,9 +11,9 @@ #include #include +#include #include #include -#include #include #include @@ -29,9 +29,7 @@ extern void stm32_power_init(void); */ void soc_early_init_hook(void) { - /* Enable instruction cache in 1-way (direct mapped cache) */ - LL_ICACHE_SetMode(LL_ICACHE_1WAY); - LL_ICACHE_Enable(); + sys_cache_instr_enable(); /* Update CMSIS SystemCoreClock variable (HCLK) */ /* At reset, system core clock is set to 32 MHz from HSI with a HSIDIV = 2 */ diff --git a/soc/st/stm32/stm32l5x/Kconfig.defconfig b/soc/st/stm32/stm32l5x/Kconfig.defconfig index 2c8607c9b79..77ba04cece9 100644 --- a/soc/st/stm32/stm32l5x/Kconfig.defconfig +++ b/soc/st/stm32/stm32l5x/Kconfig.defconfig @@ -7,6 +7,16 @@ if SOC_SERIES_STM32L5X rsource "Kconfig.defconfig.stm32l5*" +config ICACHE + default y + +config CACHE_MANAGEMENT + default y + +choice CACHE_TYPE + default EXTERNAL_CACHE +endchoice + config ROM_START_OFFSET default 0x400 if BOOTLOADER_MCUBOOT diff --git a/soc/st/stm32/stm32l5x/soc.c b/soc/st/stm32/stm32l5x/soc.c index 4c52d30bd01..d8aed0383a6 100644 --- a/soc/st/stm32/stm32l5x/soc.c +++ b/soc/st/stm32/stm32l5x/soc.c @@ -11,9 +11,9 @@ #include #include +#include #include #include -#include #include #include @@ -29,10 +29,7 @@ extern void stm32_power_init(void); */ void soc_early_init_hook(void) { - /* Enable ICACHE */ - while (LL_ICACHE_IsActiveFlag_BUSY()) { - } - LL_ICACHE_Enable(); + sys_cache_instr_enable(); /* Update CMSIS SystemCoreClock variable (HCLK) */ /* At reset, system core clock is set to 4 MHz from MSI */ diff --git a/soc/st/stm32/stm32u5x/Kconfig.defconfig b/soc/st/stm32/stm32u5x/Kconfig.defconfig index 61771d8951e..55a18e69ad0 100644 --- a/soc/st/stm32/stm32u5x/Kconfig.defconfig +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig @@ -10,6 +10,19 @@ rsource "Kconfig.defconfig.stm32u5*" config ROM_START_OFFSET default 0x400 if BOOTLOADER_MCUBOOT +config ICACHE + default y + +config DCACHE + default y + +config CACHE_MANAGEMENT + default y + +choice CACHE_TYPE + default EXTERNAL_CACHE +endchoice + if STM32_STOP3_LP_MODE config COUNTER diff --git a/soc/st/stm32/stm32u5x/power.c b/soc/st/stm32/stm32u5x/power.c index 22f12dc57bb..7ee34394883 100644 --- a/soc/st/stm32/stm32u5x/power.c +++ b/soc/st/stm32/stm32u5x/power.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include +#include #include #include #include @@ -12,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -35,22 +35,6 @@ static void pwr_stop3_isr(const struct device *dev) /* Clear all wake-up flags */ LL_PWR_ClearFlag_WU(); } - -static void disable_cache(void) -{ - /* Disabling ICACHE */ - LL_ICACHE_Disable(); - while (LL_ICACHE_IsEnabled() == 1U) { - } - - /* Wait until ICACHE_SR.BUSYF is cleared */ - while (LL_ICACHE_IsActiveFlag_BUSY() == 1U) { - } - - /* Wait until ICACHE_SR.BSYENDF is set */ - while (LL_ICACHE_IsActiveFlag_BSYEND() == 0U) { - } -} #endif void set_mode_stop(uint8_t substate_id) @@ -82,7 +66,7 @@ void set_mode_stop(uint8_t substate_id) LL_PWR_ClearFlag_SB(); LL_PWR_ClearFlag_WU(); - disable_cache(); + sys_cache_instr_disable(); LL_PWR_SetPowerMode(LL_PWR_STOP3_MODE); break; @@ -135,10 +119,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) } else if (substate_id == 4) { stm32_clock_control_standby_exit(); - LL_ICACHE_SetMode(LL_ICACHE_1WAY); - LL_ICACHE_Enable(); - while (LL_ICACHE_IsEnabled() == 0U) { - } + sys_cache_instr_enable(); LL_LPM_DisableSleepOnExit(); LL_LPM_EnableSleep(); diff --git a/soc/st/stm32/stm32u5x/soc.c b/soc/st/stm32/stm32u5x/soc.c index 131279dabae..5263db29c37 100644 --- a/soc/st/stm32/stm32u5x/soc.c +++ b/soc/st/stm32/stm32u5x/soc.c @@ -10,10 +10,10 @@ */ #include +#include #include #include #include -#include #include #include @@ -29,9 +29,7 @@ extern void stm32_power_init(void); */ void soc_early_init_hook(void) { - /* Enable instruction cache in 1-way (direct mapped cache) */ - LL_ICACHE_SetMode(LL_ICACHE_1WAY); - LL_ICACHE_Enable(); + sys_cache_instr_enable(); /* Update CMSIS SystemCoreClock variable (HCLK) */ /* At reset, system core clock is set to 4 MHz from MSIS */ diff --git a/soc/st/stm32/stm32wbax/Kconfig.defconfig b/soc/st/stm32/stm32wbax/Kconfig.defconfig index 88e41074518..498292d79ce 100644 --- a/soc/st/stm32/stm32wbax/Kconfig.defconfig +++ b/soc/st/stm32/stm32wbax/Kconfig.defconfig @@ -7,6 +7,16 @@ if SOC_SERIES_STM32WBAX rsource "Kconfig.defconfig.stm32wba*" +config ICACHE + default y + +config CACHE_MANAGEMENT + default y + +choice CACHE_TYPE + default EXTERNAL_CACHE +endchoice + config STM32_LPTIM_TIMER default y if PM diff --git a/soc/st/stm32/stm32wbax/power.c b/soc/st/stm32/stm32wbax/power.c index 6fc6e424b85..43fcd67b612 100644 --- a/soc/st/stm32/stm32wbax/power.c +++ b/soc/st/stm32/stm32wbax/power.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include +#include #include #include #include @@ -13,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -28,22 +28,6 @@ LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL); void stm32_power_init(void); -static void disable_cache(void) -{ - /* Disabling ICACHE */ - LL_ICACHE_Disable(); - while (LL_ICACHE_IsEnabled() == 1U) { - } - - /* Wait until ICACHE_SR.BUSYF is cleared */ - while (LL_ICACHE_IsActiveFlag_BUSY() == 1U) { - } - - /* Wait until ICACHE_SR.BSYENDF is set */ - while (LL_ICACHE_IsActiveFlag_BSYEND() == 0U) { - } -} - static void set_mode_stop(uint8_t substate_id) { @@ -53,7 +37,7 @@ static void set_mode_stop(uint8_t substate_id) /* Erratum 2.2.15: * Disabling ICACHE is required before entering stop mode */ - disable_cache(); + sys_cache_instr_disable(); #ifdef CONFIG_BT_STM32WBA scm_setwaitstates(LP); @@ -108,7 +92,7 @@ static void set_mode_suspend_to_ram(void) LL_PWR_ClearFlag_WU(); LL_RCC_ClearResetFlags(); - disable_cache(); + sys_cache_instr_disable(); /* Select standby mode */ LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY); @@ -161,10 +145,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) /* Erratum 2.2.15: * Enable ICACHE when exiting stop mode */ - LL_ICACHE_SetMode(LL_ICACHE_1WAY); - LL_ICACHE_Enable(); - while (LL_ICACHE_IsEnabled() == 0U) { - } + sys_cache_instr_enable(); LL_LPM_DisableSleepOnExit(); LL_LPM_EnableSleep(); diff --git a/soc/st/stm32/stm32wbax/soc.c b/soc/st/stm32/stm32wbax/soc.c index 9e49f8be955..fb54c5b5303 100644 --- a/soc/st/stm32/stm32wbax/soc.c +++ b/soc/st/stm32/stm32wbax/soc.c @@ -11,10 +11,10 @@ #include #include +#include #include #include #include -#include #include #include #include @@ -31,9 +31,7 @@ LOG_MODULE_REGISTER(soc); */ void stm32wba_init(void) { - /* Enable instruction cache in 1-way (direct mapped cache) */ - LL_ICACHE_SetMode(LL_ICACHE_1WAY); - LL_ICACHE_Enable(); + sys_cache_instr_enable(); #ifdef CONFIG_STM32_FLASH_PREFETCH __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif