From 9d81b74ff110aae6474b914349eae0b8ff5b814c Mon Sep 17 00:00:00 2001 From: Vebjorn Myklebust Date: Wed, 24 Jul 2024 14:45:52 +0200 Subject: [PATCH] drivers: pinctrl: Add support for cc23x0 pinctrl Add support for pinctrl to cc23x0 SoC. Like for other TI SoCs, a node approach is implemented (no grouping approach). Signed-off-by: Lars Thalian Morstad Signed-off-by: Vebjorn Myklebust Signed-off-by: Stoyan Bogdanov Signed-off-by: Julien Panis --- drivers/pinctrl/CMakeLists.txt | 1 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Kconfig.cc23x0 | 11 + drivers/pinctrl/pinctrl_cc23x0.c | 36 +++ dts/bindings/pinctrl/ti,cc23x0-pinctrl.yaml | 62 +++++ .../dt-bindings/pinctrl/cc23x0-pinctrl.h | 227 ++++++++++++++++++ soc/ti/simplelink/cc23x0/pinctrl_soc.h | 59 +++++ 7 files changed, 397 insertions(+) create mode 100644 drivers/pinctrl/Kconfig.cc23x0 create mode 100644 drivers/pinctrl/pinctrl_cc23x0.c create mode 100644 dts/bindings/pinctrl/ti,cc23x0-pinctrl.yaml create mode 100644 include/zephyr/dt-bindings/pinctrl/cc23x0-pinctrl.h create mode 100644 soc/ti/simplelink/cc23x0/pinctrl_soc.h diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index e56922d083e..ee17efc789f 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -21,6 +21,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX pinctrl_imx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC13XX_CC26XX pinctrl_cc13xx_cc26xx.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC23X0 pinctrl_cc23x0.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_ESP32 pinctrl_esp32.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_INFINEON_CAT1 pinctrl_ifx_cat1.c) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 299372eea7f..44bd8905643 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -50,6 +50,7 @@ source "drivers/pinctrl/Kconfig.imx" source "drivers/pinctrl/Kconfig.sifive" source "drivers/pinctrl/Kconfig.lpc_iocon" source "drivers/pinctrl/Kconfig.cc13xx_cc26xx" +source "drivers/pinctrl/Kconfig.cc23x0" source "drivers/pinctrl/Kconfig.esp32" source "drivers/pinctrl/Kconfig.rv32m1" source "drivers/pinctrl/Kconfig.ifx_cat1" diff --git a/drivers/pinctrl/Kconfig.cc23x0 b/drivers/pinctrl/Kconfig.cc23x0 new file mode 100644 index 00000000000..f10e2215aa0 --- /dev/null +++ b/drivers/pinctrl/Kconfig.cc23x0 @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_CC23X0 + bool "TI SimpleLink CC23X0 pinctrl driver" + default y + depends on DT_HAS_TI_CC23X0_PINCTRL_ENABLED + help + Enable the TI SimpleLink CC23X0 pinctrl driver diff --git a/drivers/pinctrl/pinctrl_cc23x0.c b/drivers/pinctrl/pinctrl_cc23x0.c new file mode 100644 index 00000000000..41ce0be662e --- /dev/null +++ b/drivers/pinctrl/pinctrl_cc23x0.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2024 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_cc23x0_pinctrl + +#include + +#include + +#define IOC_BASE_REG DT_REG_ADDR(DT_NODELABEL(pinctrl)) +#define IOC_BASE_PIN_REG 0x00000100 +#define IOC_ADDR(index) (IOC_BASE_REG + IOC_BASE_PIN_REG + (sizeof(uint32_t) * (index))) + +static int pinctrl_cc23x0_set(uint32_t pin, uint32_t func, uint32_t mode) +{ + uint32_t iocfg_reg = IOC_ADDR(pin); + + HWREG(iocfg_reg) = mode | func; + + return 0; +} + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + ARG_UNUSED(reg); + + for (uint8_t i = 0U; i < pin_cnt; i++) { + pinctrl_cc23x0_set(pins[i].pin, pins[i].iofunc, pins[i].iomode); + } + + return 0; +} diff --git a/dts/bindings/pinctrl/ti,cc23x0-pinctrl.yaml b/dts/bindings/pinctrl/ti,cc23x0-pinctrl.yaml new file mode 100644 index 00000000000..9f3b17221b7 --- /dev/null +++ b/dts/bindings/pinctrl/ti,cc23x0-pinctrl.yaml @@ -0,0 +1,62 @@ +# Copyright (c) 2024 Texas Instruments Incorporated +# Copyright (c) 2024 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +description: | + TI SimpleLink CC23X0 pinctrl node. + + Device pin configuration should be placed in the child nodes of this node. + Populate the 'pinmux' field with a pair consisting of a pin number and its IO + functions. + + The node has the 'pinctrl' node label set in your SoC's devicetree, + so you can modify it like this: + + &pinctrl { + /* your modifications go here */ + }; + + All device pin configurations should be placed in child nodes of the + 'pinctrl' node, as in the i2c0 example shown at the end. + + Here is a list of + supported standard pin properties: + + - bias-disable: Disable pull-up/down. + - bias-pull-down: Enable pull-down resistor. + - bias-pull-up: Enable pull-up resistor. + - drive-open-drain: Output driver is open-drain. + - drive-open-source: Output driver is open-source. + - input-enable: enable input. + - input-schmitt-enable: enable input schmitt circuit. + +compatible: "ti,cc23x0-pinctrl" + +include: base.yaml + +properties: + reg: + required: true + +child-binding: + description: | + This binding gives a base representation of the CC23X0 + pins configuration. + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-disable + - bias-pull-down + - bias-pull-up + - drive-open-drain + - drive-open-source + - input-enable + - input-schmitt-enable + + properties: + pinmux: + required: true + type: array + description: | + CC23X0 pin's configuration (IO pin, IO function). diff --git a/include/zephyr/dt-bindings/pinctrl/cc23x0-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/cc23x0-pinctrl.h new file mode 100644 index 00000000000..1c365965c9d --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/cc23x0-pinctrl.h @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2024 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef CC23X0_PINCTRL_COMMON_H_ +#define CC23X0_PINCTRL_COMMON_H_ + +/* + * The whole TI CC23X0 pin configuration information is encoded in a 32-bit + * bitfield organized as follow: + * + * - 31: Reserved + * - 30: Input hysteresis + * - 29: Input capability of IO + * - 28..27: Reserved + * - 26..24: IO mode + * - 23..22: Reserved + * - 21..20: Wakeup configuration from shutdown + * - 19: Reserved + * - 18: Wakeup capability from standby + * - 17..16: Edge detection configuration + * - 15: Reserved + * - 14..13: Pull control + * - 12..3: Reserved + * - 2..0: Function configuration + */ + +/* TI CC23X0 function configuration */ + +#define IOC_PORTCFG_BASE 0U +#define IOC_PORTCFG_PFUNC1 1U +#define IOC_PORTCFG_PFUNC2 2U +#define IOC_PORTCFG_PFUNC3 3U +#define IOC_PORTCFG_PFUNC4 4U +#define IOC_PORTCFG_PFUNC5 5U +#define IOC_PORTCFG_ANA 6U +#define IOC_PORTCFG_DTB 7U + +/* TI CC23X0 peripheral pin mapping */ + +#define DIO0_GPIO0 IOC_PORTCFG_BASE +#define DIO0_SPI0_CSN IOC_PORTCFG_PFUNC1 +#define DIO0_I2C0_SDA IOC_PORTCFG_PFUNC2 +#define DIO0_T3_C2 IOC_PORTCFG_PFUNC3 +#define DIO0_ADC5 IOC_PORTCFG_ANA + +#define DIO1_GPIO1 IOC_PORTCFG_BASE +#define DIO1_T3_C1 IOC_PORTCFG_PFUNC1 +#define DIO1_LRFD7 IOC_PORTCFG_PFUNC2 +#define DIO1_T1_F IOC_PORTCFG_PFUNC3 +#define DIO1_UART0_RTS IOC_PORTCFG_PFUNC4 +#define DIO1_ADC4 IOC_PORTCFG_ANA +#define DIO1_DTB2 IOC_PORTCFG_DTB + +#define DIO2_GPIO2 IOC_PORTCFG_BASE +#define DIO2_T0_PE IOC_PORTCFG_PFUNC1 +#define DIO2_T2_C1N IOC_PORTCFG_PFUNC2 +#define DIO2_UART0_CTS IOC_PORTCFG_PFUNC3 +#define DIO2_ADC3 IOC_PORTCFG_ANA + +#define DIO3_GPIO3 IOC_PORTCFG_BASE +#define DIO3_LFCI IOC_PORTCFG_PFUNC1 +#define DIO3_T0_C1N IOC_PORTCFG_PFUNC2 +#define DIO3_LRFD0 IOC_PORTCFG_PFUNC3 +#define DIO3_T3_C1 IOC_PORTCFG_PFUNC4 +#define DIO3_T1_C2 IOC_PORTCFG_PFUNC5 +#define DIO3_LFXT_P IOC_PORTCFG_ANA +#define DIO3_DTB7 IOC_PORTCFG_DTB + +#define DIO4_GPIO4 IOC_PORTCFG_BASE +#define DIO4_T0_C2N IOC_PORTCFG_PFUNC1 +#define DIO4_UART0_TXD IOC_PORTCFG_PFUNC2 +#define DIO4_LRFD1 IOC_PORTCFG_PFUNC3 +#define DIO4_SPI0_MOSI IOC_PORTCFG_PFUNC4 +#define DIO4_T0_C2 IOC_PORTCFG_PFUNC5 +#define DIO4_LFXT_N IOC_PORTCFG_ANA +#define DIO4_DTB8 IOC_PORTCFG_DTB + +#define DIO5_GPIO5 IOC_PORTCFG_BASE +#define DIO5_T2_C2 IOC_PORTCFG_PFUNC1 +#define DIO5_LRFD6 IOC_PORTCFG_PFUNC3 +#define DIO5_ADC2 IOC_PORTCFG_ANA + +#define DIO6_GPIO6 IOC_PORTCFG_BASE +#define DIO6_SPI0_CSN IOC_PORTCFG_PFUNC1 +#define DIO6_I2C0_SCL IOC_PORTCFG_PFUNC2 +#define DIO6_T1_C2 IOC_PORTCFG_PFUNC3 +#define DIO6_LRFD2 IOC_PORTCFG_PFUNC4 +#define DIO6_UART0_TXD IOC_PORTCFG_PFUNC5 +#define DIO6_ADC1_AREFP IOC_PORTCFG_ANA +#define DIO6_DTB6 IOC_PORTCFG_DTB + +#define DIO7_GPIO7 IOC_PORTCFG_BASE +#define DIO7_T3_C1 IOC_PORTCFG_PFUNC1 +#define DIO7_LRFD4 IOC_PORTCFG_PFUNC3 +#define DIO7_ADC0_AREFM IOC_PORTCFG_ANA + +#define DIO8_GPIO8 IOC_PORTCFG_BASE +#define DIO8_SPI0_SCLK IOC_PORTCFG_PFUNC1 +#define DIO8_UART0_RTS IOC_PORTCFG_PFUNC2 +#define DIO8_T1_C0N IOC_PORTCFG_PFUNC3 +#define DIO8_I2C0_SDA IOC_PORTCFG_PFUNC4 +#define DIO8_T0_C0N IOC_PORTCFG_PFUNC5 +#define DIO8_DTB3 IOC_PORTCFG_DTB + +#define DIO9_GPIO9 IOC_PORTCFG_BASE +#define DIO9_T3_C0 IOC_PORTCFG_PFUNC1 +#define DIO9_LRFD3 IOC_PORTCFG_PFUNC3 + +#define DIO10_GPIO10 IOC_PORTCFG_BASE +#define DIO10_LPC0 IOC_PORTCFG_PFUNC1 +#define DIO10_T2_PE IOC_PORTCFG_PFUNC2 +#define DIO10_T3_C0N IOC_PORTCFG_PFUNC3 + +#define DIO11_GPIO11 IOC_PORTCFG_BASE +#define DIO11_SPI0_CSN IOC_PORTCFG_PFUNC1 +#define DIO11_T1_C2N IOC_PORTCFG_PFUNC2 +#define DIO11_T0_C0 IOC_PORTCFG_PFUNC3 +#define DIO11_LRFD0 IOC_PORTCFG_PFUNC4 +#define DIO11_SPI0_MISO IOC_PORTCFG_PFUNC5 +#define DIO11_DTB9 IOC_PORTCFG_DTB + +#define DIO12_GPIO12 IOC_PORTCFG_BASE +#define DIO12_SPI0_MISO IOC_PORTCFG_PFUNC1 +#define DIO12_SPI0_MOSI IOC_PORTCFG_PFUNC2 +#define DIO12_UART0_RXD IOC_PORTCFG_PFUNC3 +#define DIO12_T1_C1 IOC_PORTCFG_PFUNC4 +#define DIO12_I2C0_SDA IOC_PORTCFG_PFUNC5 +#define DIO12_DTB13 IOC_PORTCFG_DTB + +#define DIO13_GPIO13 IOC_PORTCFG_BASE +#define DIO13_SPI0_MISO IOC_PORTCFG_PFUNC1 +#define DIO13_SPI0_MOSI IOC_PORTCFG_PFUNC2 +#define DIO13_UART0_TXD IOC_PORTCFG_PFUNC3 +#define DIO13_T0_C0N IOC_PORTCFG_PFUNC4 +#define DIO13_T1_F IOC_PORTCFG_PFUNC5 +#define DIO13_DTB4 IOC_PORTCFG_DTB + +#define DIO14_GPIO14 IOC_PORTCFG_BASE +#define DIO14_T3_C2 IOC_PORTCFG_PFUNC1 +#define DIO14_T1_C2N IOC_PORTCFG_PFUNC2 +#define DIO14_LRFD5 IOC_PORTCFG_PFUNC3 +#define DIO14_T1_F IOC_PORTCFG_PFUNC4 + +#define DIO15_GPIO15 IOC_PORTCFG_BASE +#define DIO15_UART0_RXD IOC_PORTCFG_PFUNC1 +#define DIO15_T2_C0N IOC_PORTCFG_PFUNC2 +#define DIO15_CKMIN IOC_PORTCFG_PFUNC3 + +#define DIO16_GPIO16 IOC_PORTCFG_BASE +#define DIO16_SPI0_MOSI IOC_PORTCFG_PFUNC1 +#define DIO16_UART0_RXD IOC_PORTCFG_PFUNC2 +#define DIO16_I2C0_SDA IOC_PORTCFG_PFUNC3 +#define DIO16_T1_C2 IOC_PORTCFG_PFUNC4 +#define DIO16_T1_C0N IOC_PORTCFG_PFUNC5 +#define DIO16_DTB10 IOC_PORTCFG_DTB + +#define DIO17_GPIO17 IOC_PORTCFG_BASE +#define DIO17_SPI0_SCLK IOC_PORTCFG_PFUNC1 +#define DIO17_UART0_TXD IOC_PORTCFG_PFUNC2 +#define DIO17_I2C0_SCL IOC_PORTCFG_PFUNC3 +#define DIO17_T1_C1N IOC_PORTCFG_PFUNC4 +#define DIO17_T0_C2 IOC_PORTCFG_PFUNC5 +#define DIO17_DTB11 IOC_PORTCFG_DTB + +#define DIO18_GPIO18 IOC_PORTCFG_BASE +#define DIO18_T3_C0 IOC_PORTCFG_PFUNC1 +#define DIO18_LPC0 IOC_PORTCFG_PFUNC2 +#define DIO18_UART0_TXD IOC_PORTCFG_PFUNC3 +#define DIO18_SPI0_SCLK IOC_PORTCFG_PFUNC4 +#define DIO18_DTB12 IOC_PORTCFG_DTB + +#define DIO19_GPIO19 IOC_PORTCFG_BASE +#define DIO19_T3_C1 IOC_PORTCFG_PFUNC1 +#define DIO19_T2_PE IOC_PORTCFG_PFUNC2 +#define DIO19_SPI0_MOSI IOC_PORTCFG_PFUNC4 +#define DIO19_DTB0 IOC_PORTCFG_DTB + +#define DIO20_GPIO20 IOC_PORTCFG_BASE +#define DIO20_LPC0 IOC_PORTCFG_PFUNC1 +#define DIO20_UART0_TXD IOC_PORTCFG_PFUNC2 +#define DIO20_UART0_RXD IOC_PORTCFG_PFUNC3 +#define DIO20_T1_C0 IOC_PORTCFG_PFUNC4 +#define DIO20_SPI0_MISO IOC_PORTCFG_PFUNC5 +#define DIO20_ADC11 IOC_PORTCFG_ANA +#define DIO20_DTB14 IOC_PORTCFG_DTB + +#define DIO21_GPIO21 IOC_PORTCFG_BASE +#define DIO21_UART0_CTS IOC_PORTCFG_PFUNC1 +#define DIO21_T1_C1N IOC_PORTCFG_PFUNC2 +#define DIO21_T0_C1 IOC_PORTCFG_PFUNC3 +#define DIO21_SPI0_MISO IOC_PORTCFG_PFUNC4 +#define DIO21_LRFD1 IOC_PORTCFG_PFUNC5 +#define DIO21_ADC10_LPCP IOC_PORTCFG_ANA +#define DIO21_DTB15 IOC_PORTCFG_DTB + +#define DIO22_GPIO22 IOC_PORTCFG_BASE +#define DIO22_T2_C0 IOC_PORTCFG_PFUNC1 +#define DIO22_UART0_RXD IOC_PORTCFG_PFUNC2 +#define DIO22_T3_C1N IOC_PORTCFG_PFUNC3 +#define DIO22_ADC9 IOC_PORTCFG_ANA +#define DIO22_DTB1 IOC_PORTCFG_DTB + +#define DIO23_GPIO23 IOC_PORTCFG_BASE +#define DIO23_T2_C1 IOC_PORTCFG_PFUNC1 +#define DIO23_T3_C2N IOC_PORTCFG_PFUNC3 +#define DIO23_ADC8_LPCP_LPCM IOC_PORTCFG_ANA + +#define DIO24_GPIO24 IOC_PORTCFG_BASE +#define DIO24_SPI0_SCLK IOC_PORTCFG_PFUNC1 +#define DIO24_T1_C0 IOC_PORTCFG_PFUNC2 +#define DIO24_T3_C0 IOC_PORTCFG_PFUNC3 +#define DIO24_T0_PE IOC_PORTCFG_PFUNC4 +#define DIO24_I2C0_SCL IOC_PORTCFG_PFUNC5 +#define DIO24_ADC7_LPCP_LPCM IOC_PORTCFG_ANA +#define DIO24_DTB5 IOC_PORTCFG_DTB + +#define DIO25_GPIO25 IOC_PORTCFG_BASE +#define DIO25_SPI0_MISO IOC_PORTCFG_PFUNC1 +#define DIO25_I2C0_SCL IOC_PORTCFG_PFUNC2 +#define DIO25_T2_C2N IOC_PORTCFG_PFUNC3 +#define DIO25_ADC6 IOC_PORTCFG_ANA + +#endif /* CC23X0_PINCTRL_COMMON_H_ */ diff --git a/soc/ti/simplelink/cc23x0/pinctrl_soc.h b/soc/ti/simplelink/cc23x0/pinctrl_soc.h new file mode 100644 index 00000000000..4c2c6fefd16 --- /dev/null +++ b/soc/ti/simplelink/cc23x0/pinctrl_soc.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2024 Texas Instruments Incorporated + * Copyright (c) 2024 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef TI_SIMPLELINK_CC23X0_SOC_PINCTRL_H_ +#define TI_SIMPLELINK_CC23X0_SOC_PINCTRL_H_ + +#include + +/* IO enabling/disabling */ +#define IOC_INPUT_ENABLE BIT(29) +#define IOC_INPUT_DISABLE 0U +#define IOC_HYST_ENABLE BIT(30) +#define IOC_HYST_DISABLE 0U + +/* IO modes */ +#define IOC_IOMODE_NORMAL 0U +#define IOC_IOMODE_INV BIT(24) +#define IOC_IOMODE_OPEN_DRAIN_NORMAL BIT(25) +#define IOC_IOMODE_OPEN_DRAIN_INV GENMASK(25, 24) +#define IOC_IOMODE_OPEN_SRC_NORMAL BIT(26) +#define IOC_IOMODE_OPEN_SRC_INV (BIT(26) | BIT(24)) + +/* IO pull */ +#define IOC_NO_IOPULL 0U +#define IOC_IOPULL_UP BIT(14) +#define IOC_IOPULL_DOWN BIT(13) + +typedef struct pinctrl_soc_pin { + uint32_t pin; + uint32_t iofunc; + uint32_t iomode; +} pinctrl_soc_pin_t; + +/* Convert DT flags to SoC flags */ +#define CC23X0_PIN_FLAGS(node_id) \ + (DT_PROP(node_id, bias_pull_up) * IOC_IOPULL_UP | \ + DT_PROP(node_id, bias_pull_down) * IOC_IOPULL_DOWN | \ + DT_PROP(node_id, bias_disable) * IOC_NO_IOPULL | \ + DT_PROP(node_id, drive_open_drain) * IOC_IOMODE_OPEN_DRAIN_NORMAL | \ + DT_PROP(node_id, drive_open_source) * IOC_IOMODE_OPEN_SRC_NORMAL | \ + DT_PROP(node_id, input_enable) * IOC_INPUT_ENABLE | \ + DT_PROP(node_id, input_schmitt_enable) * IOC_HYST_ENABLE) + +#define CC23X0_DT_PIN(node_id) \ + {.pin = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .iofunc = DT_PROP_BY_IDX(node_id, pinmux, 1), \ + .iomode = CC23X0_PIN_FLAGS(node_id)}, + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + CC23X0_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)) + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)} + +#endif /* TI_SIMPLELINK_CC23X0_SOC_PINCTRL_H_ */