michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: arm: nxp: remove custom fixed MPU region definition

Browse source 
We remove the custom fixed MPU region definition from NXP IMX
RT, Kinetis, and LPC SoC definitions, as the common fixed MPU
region definition is now used.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit is contained in:
Ioannis Glaropoulos 2019-12-06 10:26:06 +01:00 • committed by Anas Nashif
commit 9ce4d8f20d
9 changed files with 0 additions and 235 deletions
Download patch file Download diff file Expand all files Collapse all files

2
soc/arm/nxp_imx/rt/CMakeLists.txt
View file

@ -7,5 +7,3 @@
zephyr_sources(
soc.c
)
zephyr_sources_ifdef(CONFIG_ARM_MPU arm_mpu_regions.c)

58
soc/arm/nxp_imx/rt/arm_mpu_mem_cfg.h
View file

@ -1,58 +0,0 @@
/*
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _IMX_RT_MPU_MEM_CFG_H_
#define _IMX_RT_MPU_MEM_CFG_H_
#include <soc.h>
#include <arch/arm/cortex_m/mpu/arm_mpu.h>
/* Flash Region Definitions */
#if CONFIG_FLASH_SIZE == 32
#define REGION_FLASH_SIZE REGION_32K
#elif CONFIG_FLASH_SIZE == 64
#define REGION_FLASH_SIZE REGION_64K
#elif CONFIG_FLASH_SIZE == 128
#define REGION_FLASH_SIZE REGION_128K
#elif CONFIG_FLASH_SIZE == 256
#define REGION_FLASH_SIZE REGION_256K
#elif CONFIG_FLASH_SIZE == 512
#define REGION_FLASH_SIZE REGION_512K
#elif CONFIG_FLASH_SIZE == 1024
#define REGION_FLASH_SIZE REGION_1M
#elif CONFIG_FLASH_SIZE == 2048
#define REGION_FLASH_SIZE REGION_2M
#elif CONFIG_FLASH_SIZE == 4096
#define REGION_FLASH_SIZE REGION_4M
#elif CONFIG_FLASH_SIZE == 8192
#define REGION_FLASH_SIZE REGION_8M
#elif CONFIG_FLASH_SIZE == 16384
#define REGION_FLASH_SIZE REGION_16M
#elif CONFIG_FLASH_SIZE == 65536
#define REGION_FLASH_SIZE REGION_64M
#else
#error "Unsupported configuration"
#endif
/* SRAM Region Definitions */
#if CONFIG_SRAM_SIZE == 32
#define REGION_SRAM_0_SIZE REGION_32K
#elif CONFIG_SRAM_SIZE == 64
#define REGION_SRAM_0_SIZE REGION_64K
#elif CONFIG_SRAM_SIZE == 128
#define REGION_SRAM_0_SIZE REGION_128K
#elif CONFIG_SRAM_SIZE == 256
#define REGION_SRAM_0_SIZE REGION_256K
#elif CONFIG_SRAM_SIZE == 512
#define REGION_SRAM_0_SIZE REGION_512K
#elif CONFIG_SRAM_SIZE == 768
#define REGION_SRAM_0_SIZE REGION_1M /* MPU expects power of two size */
#elif CONFIG_SRAM_SIZE == 32768
#define REGION_SRAM_0_SIZE REGION_32M
#else
#error "Unsupported configuration"
#endif
#endif /* _IMX_RT_MPU_MEM_CFG_H_ */

29
soc/arm/nxp_imx/rt/arm_mpu_regions.c
View file

@ -1,29 +0,0 @@
/*
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <arch/arm/cortex_m/mpu/arm_mpu.h>
#include "arm_mpu_mem_cfg.h"
#define PERIPH_BASE 0x40000000
#define PPB_BASE 0xE0000000
static const struct arm_mpu_region mpu_regions[] = {
/* Region 0 */
MPU_REGION_ENTRY("FLASH_0",
CONFIG_FLASH_BASE_ADDRESS,
REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
/* Region 1 */
MPU_REGION_ENTRY("SRAM_0",
CONFIG_SRAM_BASE_ADDRESS,
REGION_RAM_ATTR(REGION_SRAM_0_SIZE)),
};
const struct arm_mpu_config mpu_config = {
.num_regions = ARRAY_SIZE(mpu_regions),
.mpu_regions = mpu_regions,
};

4
soc/arm/nxp_kinetis/kv5x/CMakeLists.txt
View file

@ -4,7 +4,3 @@ zephyr_sources(
soc.c
wdog.S
)
zephyr_sources_ifdef(
CONFIG_ARM_MPU
arm_mpu_regions.c
)

30
soc/arm/nxp_kinetis/kv5x/arm_mpu_mem_cfg.h
View file

@ -1,30 +0,0 @@
/*
* Copyright (c) 2017 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ARM_MPU_MEM_CFG_H_
#define _ARM_MPU_MEM_CFG_H_
#include <soc.h>
#include <arch/arm/cortex_m/mpu/arm_mpu.h>
/* Flash Region Definitions */
#if CONFIG_FLASH_SIZE == 512
#define REGION_FLASH_SIZE REGION_512K
#elif CONFIG_FLASH_SIZE == 1024
#define REGION_FLASH_SIZE REGION_1M
#else
#error "Unsupported configuration"
#endif
/* SRAM Region Definitions */
#if CONFIG_SRAM_SIZE == 64
#define REGION_SRAM_0_SIZE REGION_64K
#elif CONFIG_SRAM_SIZE == 128
#define REGION_SRAM_0_SIZE REGION_128K
#else
#error "Unsupported configuration"
#endif
#endif /* _ARM_MPU_MEM_CFG_H_ */

26
soc/arm/nxp_kinetis/kv5x/arm_mpu_regions.c
View file

@ -1,26 +0,0 @@
/*
* Copyright (c) 2017 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <arch/arm/cortex_m/mpu/arm_mpu.h>
#include "arm_mpu_mem_cfg.h"
static const struct arm_mpu_region mpu_regions[] = {
/* Region 0 */
MPU_REGION_ENTRY("FLASH_0",
CONFIG_FLASH_BASE_ADDRESS,
REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
/* Region 1 */
MPU_REGION_ENTRY("SRAM_0",
CONFIG_SRAM_BASE_ADDRESS,
REGION_RAM_ATTR(REGION_SRAM_0_SIZE)),
};
const struct arm_mpu_config mpu_config = {
.num_regions = ARRAY_SIZE(mpu_regions),
.mpu_regions = mpu_regions,
};

2
soc/arm/nxp_lpc/lpc54xxx/CMakeLists.txt
View file

@ -7,8 +7,6 @@ zephyr_library()
zephyr_library_sources(soc.c)
zephyr_sources_ifdef(CONFIG_ARM_MPU arm_mpu_regions.c)
zephyr_library_include_directories(
${ZEPHYR_BASE}/kernel/include
${ZEPHYR_BASE}/arch/${ARCH}/include

58
soc/arm/nxp_lpc/lpc54xxx/arm_mpu_mem_cfg.h
View file

@ -1,58 +0,0 @@
/*
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ARM_MPU_MEM_CFG_H_
#define _ARM_MPU_MEM_CFG_H_
#include <soc.h>
#include <arch/arm/cortex_m/mpu/arm_mpu.h>
/* Flash Region Definitions */
#if CONFIG_FLASH_SIZE == 32
#define REGION_FLASH_SIZE REGION_32K
#elif CONFIG_FLASH_SIZE == 64
#define REGION_FLASH_SIZE REGION_64K
#elif CONFIG_FLASH_SIZE == 128
#define REGION_FLASH_SIZE REGION_128K
#elif CONFIG_FLASH_SIZE == 256
#define REGION_FLASH_SIZE REGION_256K
#elif CONFIG_FLASH_SIZE == 512
#define REGION_FLASH_SIZE REGION_512K
#elif CONFIG_FLASH_SIZE == 1024
#define REGION_FLASH_SIZE REGION_1M
#elif CONFIG_FLASH_SIZE == 2048
#define REGION_FLASH_SIZE REGION_2M
#elif CONFIG_FLASH_SIZE == 4096
#define REGION_FLASH_SIZE REGION_4M
#elif CONFIG_FLASH_SIZE == 8192
#define REGION_FLASH_SIZE REGION_8M
#elif CONFIG_FLASH_SIZE == 16384
#define REGION_FLASH_SIZE REGION_16M
#elif CONFIG_FLASH_SIZE == 65536
#define REGION_FLASH_SIZE REGION_64M
#else
#error "Unsupported configuration"
#endif
/* SRAM Region Definitions */
#if CONFIG_SRAM_SIZE == 32
#define REGION_SRAM_0_SIZE REGION_32K
#elif CONFIG_SRAM_SIZE == 64
#define REGION_SRAM_0_SIZE REGION_64K
#elif CONFIG_SRAM_SIZE == 128
#define REGION_SRAM_0_SIZE REGION_128K
#elif CONFIG_SRAM_SIZE == 256
#define REGION_SRAM_0_SIZE REGION_256K
#elif CONFIG_SRAM_SIZE == 512
#define REGION_SRAM_0_SIZE REGION_512K
#elif CONFIG_SRAM_SIZE == 768
#define REGION_SRAM_0_SIZE REGION_1M /* MPU expects power of two size */
#elif CONFIG_SRAM_SIZE == 32768
#define REGION_SRAM_0_SIZE REGION_32M
#else
#error "Unsupported configuration"
#endif
#endif /* _ARM_MPU_MEM_CFG_H_ */

26
soc/arm/nxp_lpc/lpc54xxx/arm_mpu_regions.c
View file

@ -1,26 +0,0 @@
/*
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <arch/arm/cortex_m/mpu/arm_mpu.h>
#include "arm_mpu_mem_cfg.h"
static const struct arm_mpu_region mpu_regions[] = {
/* Region 0 */
MPU_REGION_ENTRY("FLASH_0",
CONFIG_FLASH_BASE_ADDRESS,
REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
/* Region 1 */
MPU_REGION_ENTRY("SRAM_0",
CONFIG_SRAM_BASE_ADDRESS,
REGION_RAM_ATTR(REGION_SRAM_0_SIZE)),
};
const struct arm_mpu_config mpu_config = {
.num_regions = ARRAY_SIZE(mpu_regions),
.mpu_regions = mpu_regions,
};