michaelh/zephyr
1
0
Fork 0
Code Releases Activity

pci: add Extended PCI(e) capability offset get

Browse source 
Extend the PCIe API to find Extended Capabilities in the PCI Express
Extended Capabilities located in Configuration Space at offsets 256
or greater.

Note: the Root Complex Register Block is not supported

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong 2021-07-02 16:40:49 +02:00 • committed by Anas Nashif
commit 99c2279abf
2 changed files with 49 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

24
include/drivers/pcie/pcie.h
View file

@ -167,6 +167,15 @@ extern void pcie_irq_enable(pcie_bdf_t bdf, unsigned int irq);
*/
extern uint32_t pcie_get_cap(pcie_bdf_t bdf, uint32_t cap_id);
/**
* @brief Find an Extended PCI(e) capability in an endpoint's configuration space.
*
* @param bdf the PCI endpoint to examine
* @param cap_id the capability ID of interest
* @return the index of the configuration word, or 0 if no capability.
*/
extern uint32_t pcie_get_ext_cap(pcie_bdf_t bdf, uint32_t cap_id);
/*
* Configuration word 13 contains the head of the capabilities list.
*/
@ -182,6 +191,21 @@ extern uint32_t pcie_get_cap(pcie_bdf_t bdf, uint32_t cap_id);
#define PCIE_CONF_CAP_ID(w) ((w) & 0xFFU)
#define PCIE_CONF_CAP_NEXT(w) (((w) >> 10) & 0x3FU)
/*
* The extended PCI Express capabilies lies at the end of the PCI configuration space
*/
#define PCIE_CONF_EXT_CAPPTR 64U
/*
* The first word of every capability contains an extended capability identifier,
* and a link to the next capability (or 0) in the extended configuration space.
*/
#define PCIE_CONF_EXT_CAP_ID(w) ((w) & 0xFFFFU)
#define PCIE_CONF_EXT_CAP_VER(w) (((w) >> 16) & 0xFU)
#define PCIE_CONF_EXT_CAP_NEXT(w) (((w) >> 20) & 0xFFFU)
/*
* Configuration word 0 aligns directly with pcie_id_t.
*/