arch: xtensa: Move exception table to xtensa_intr.c
This cleans up the exception handling by removing the table declaration from xtensa_intr_asm.S, and removing the unused _xt_set_exception_handler() function. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
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27ea2d8eb7
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15 changed files with 17 additions and 68 deletions
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@ -17,44 +17,15 @@
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#include <sw_isr_table.h>
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#if XCHAL_HAVE_EXCEPTIONS
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/* Handler table is in xtensa_intr_asm.S */
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extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM];
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/*
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* Default handler for unhandled exceptions.
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*/
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void xt_unhandled_exception(XtExcFrame *frame)
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static void unhandled_exception_trampoline(XtExcFrame *frame)
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{
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FatalErrorHandler();
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CODE_UNREACHABLE;
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}
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/*
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* This function registers a handler for the specified exception.
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* The function returns the address of the previous handler.
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* On error, it returns 0.
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*/
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xt_exc_handler _xt_set_exception_handler(int n, xt_exc_handler f)
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{
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xt_exc_handler old;
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if (n < 0 || n >= XCHAL_EXCCAUSE_NUM)
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return 0; /* invalid exception number */
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old = _xt_exception_table[n];
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if (f) {
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_xt_exception_table[n] = f;
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} else {
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_xt_exception_table[n] = &xt_unhandled_exception;
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}
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return ((old == &xt_unhandled_exception) ? 0 : old);
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}
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xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM] __aligned(4) = {
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[0 ... (XCHAL_EXCCAUSE_NUM - 1)] = unhandled_exception_trampoline
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};
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#endif
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#if defined(CONFIG_SW_ISR_TABLE) && defined(XCHAL_HAVE_INTERRUPTS)
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@ -39,28 +39,6 @@ _xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */
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#endif /* XCHAL_HAVE_INTERRUPTS */
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#if XCHAL_HAVE_EXCEPTIONS
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/*
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-------------------------------------------------------------------------------
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Table of C-callable exception handlers for each exception. Note that not all
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slots will be active, because some exceptions (e.g. coprocessor exceptions)
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are always handled by the OS and cannot be hooked by user handlers.
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-------------------------------------------------------------------------------
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*/
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.data
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.global _xt_exception_table
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.align 4
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_xt_exception_table:
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.rept XCHAL_EXCCAUSE_NUM
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.word xt_unhandled_exception /* handler address */
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.endr
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#endif
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/*
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-------------------------------------------------------------------------------
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unsigned int _xt_ints_on ( unsigned int mask )
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@ -50,7 +50,7 @@ MEMORY
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srom1_seg : org = 0x50000300, len = 0xFFFD00
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sram0_seg : org = 0x60000000, len = 0x4000000
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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IDT_LIST : org = 0x3ffbe000, len = 0x2000
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#endif
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}
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@ -50,7 +50,7 @@ MEMORY
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sram18_seg : org = 0x600003C0, len = 0x40
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sram19_seg : org = 0x60000400, len = 0x3FFFC00
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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IDT_LIST : org = 0x3ffbe000, len = 0x2000
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#endif
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}
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@ -47,7 +47,7 @@ MEMORY
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srom0_seg : org = 0xFE000000, len = 0x300
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srom1_seg : org = 0xFE000300, len = 0xFFFD00
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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IDT_LIST : org = 0x3ffdd50, len = 0x2000
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#endif
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}
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@ -50,7 +50,7 @@ MEMORY
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sram18_seg : org = 0x6000027C, len = 0x1C
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sram19_seg : org = 0x60000298, len = 0x3FFFD68
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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IDT_LIST : org = 0x3fffe000, len = 0x2000
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#endif
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}
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@ -35,7 +35,7 @@ MEMORY
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srom1_seg : org = 0x50000300, len = 0xFFFD00
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sram0_seg : org = 0x60000000, len = 0x4000000
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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IDT_LIST : org = 0x3ffde000, len = 0x2000
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#endif
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}
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@ -38,7 +38,7 @@ MEMORY
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rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000
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rtc_slow_seg(RW): org = 0x50000000, len = 0x1000
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST(RW): org = 0xffffdfff, len = 0x2000
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IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
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#endif
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}
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@ -50,7 +50,7 @@ MEMORY
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sram18_seg : org = 0x600003C0, len = 0x40
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sram19_seg : org = 0x60000400, len = 0x3FFFC00
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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IDT_LIST : org = 0x3ffbe000, len = 0x2000
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#endif
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}
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@ -37,7 +37,7 @@ MEMORY
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sram8_seg : org = 0x600001DC, len = 0x1C
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sram9_seg : org = 0x600001F8, len = 0x3FFFE08
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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IDT_LIST : org = 0x4fffe000, len = 0x2000
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#endif
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}
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@ -37,7 +37,7 @@ MEMORY
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sram8_seg : org = 0x600001DC, len = 0x1C
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sram9_seg : org = 0x600001F8, len = 0x3FFFE08
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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IDT_LIST : org = 0x4fffe000, len = 0x2000
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#endif
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}
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@ -41,7 +41,7 @@ MEMORY
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sram12_seg : org = 0x60000300, len = 0x40
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sram13_seg : org = 0x60000340, len = 0x3FFCC0
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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IDT_LIST : org = 0x4fffe000, len = 0x2000
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#endif
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}
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@ -34,7 +34,7 @@ MEMORY
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iram0_6_seg : org = 0x60020324, len = 0x1C
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iram0_7_seg : org = 0x60020340, len = 0x1FCC0
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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IDT_LIST : org = 0x5fffe000, len = 0x2000
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#endif
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}
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@ -34,7 +34,7 @@ MEMORY
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iram0_6_seg : org = 0x60020324, len = 0x1C
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iram0_7_seg : org = 0x60020340, len = 0x1FCC0
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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IDT_LIST : org = 0x5fffe000, len = 0x2000
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#endif
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}
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@ -50,7 +50,7 @@ MEMORY
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srom1_seg : org = 0x50000300, len = 0xFFFD00
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sram0_seg : org = 0x60000000, len = 0x4000000
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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IDT_LIST : org = 0x3ffbe000, len = 0x2000
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#endif
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}
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