michaelh/zephyr
1
0
Fork 0
Code Releases Activity

dts: xtensa: Add device tree support for xtensa

Browse source 
Change-Id: I309bc50c6b575caa84fbc7ab98cc9890771b4274
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
This commit is contained in:
Savinay Dharmappa 2018-03-21 19:58:06 +05:30 • committed by Anas Nashif
commit 97f721d928
8 changed files with 81 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

11
arch/xtensa/soc/intel_s1000/dts.fixup Normal file
View file

@ -0,0 +1,11 @@
/* SoC level DTS fixup file */
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_80800_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_80800_LABEL
#define L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define L2_SRAM_SIZE CONFIG_SRAM_SIZE_0 * 1024
/* End of SoC Level DTS fixup file */

1
arch/xtensa/soc/intel_s1000/linker.ld
View file

@ -15,6 +15,7 @@ OUTPUT_ARCH(xtensa)
#define _LINKER #define _LINKER
#define _ASMLANGUAGE #define _ASMLANGUAGE
#include <generated_dts_board.h>
#include "memory.h" #include "memory.h"
#include <autoconf.h> #include <autoconf.h>
#include <linker/sections.h> #include <linker/sections.h>

2
arch/xtensa/soc/intel_s1000/memory.h
View file

@ -7,8 +7,6 @@
#define __INC_MEMORY_H #define __INC_MEMORY_H
/* L2 HP SRAM */ /* L2 HP SRAM */
#define L2_SRAM_BASE 0xBE000000
#define L2_SRAM_SIZE 0x00300000
#define L2_VECTOR_SIZE 0x1000 #define L2_VECTOR_SIZE 0x1000
/* The reset vector address in SRAM and its size */ /* The reset vector address in SRAM and its size */

1
boards/xtensa/intel_s1000_crb/Kconfig.board
View file

@ -6,3 +6,4 @@
config BOARD_INTEL_S1000_CRB config BOARD_INTEL_S1000_CRB
bool "Xtensa on Intel_S1000" bool "Xtensa on Intel_S1000"
depends on SOC_INTEL_S1000 depends on SOC_INTEL_S1000
select HAS_DTS

4
boards/xtensa/intel_s1000_crb/Kconfig.defconfig
View file

@ -82,10 +82,6 @@ config UART_NS16550_PORT_0
if UART_NS16550_PORT_0 if UART_NS16550_PORT_0
config UART_NS16550_PORT_0_NAME
default "UART_0"
config UART_NS16550_PORT_0_BAUD_RATE
default 115200
config UART_NS16550_PORT_0_OPTIONS config UART_NS16550_PORT_0_OPTIONS
default 0 default 0
config UART_INTERRUPT_DRIVEN config UART_INTERRUPT_DRIVEN

23
boards/xtensa/intel_s1000_crb/intel_s1000_crb.dts Normal file
View file

@ -0,0 +1,23 @@
/dts-v1/;
#include "intel_s1000.dtsi"
/ {
model = "intel_s1000_crb";
compatible = "intel,s1000";
aliases {
uart_0 = &uart0;
};
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart0;
};
};
&uart0 {
status = "ok";
current-speed = <115200>;
};

44
dts/xtensa/intel_s1000.dtsi Normal file
View file

@ -0,0 +1,44 @@
#include "skeleton.dtsi"
#define __SIZE_K(x) (x * 1024)
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "LX6";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "LX6";
reg = <1>;
};
};
sram0: memory@0xbe000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0xbe000000 0x300000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
uart0: uart@80800 {
compatible = "ns16550";
reg = <0x80800 0x400>;
label = "UART_0";
status = "disabled";
};
};
};

1
include/arch/xtensa/arch.h
View file

@ -19,6 +19,7 @@
extern "C" { extern "C" {
#endif #endif
#include <generated_dts_board.h>
#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) #if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
#include "sys_io.h" /* Include from the very same folder of this file */ #include "sys_io.h" /* Include from the very same folder of this file */
#include <zephyr/types.h> #include <zephyr/types.h>