diff --git a/arch/xtensa/soc/intel_s1000/dts.fixup b/arch/xtensa/soc/intel_s1000/dts.fixup
new file mode 100644
index 00000000000..ba77b146d52
--- /dev/null
+++ b/arch/xtensa/soc/intel_s1000/dts.fixup
@@ -0,0 +1,11 @@
+/* SoC level DTS fixup file */
+
+#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE	NS16550_80800_CURRENT_SPEED
+
+#define CONFIG_UART_NS16550_PORT_0_NAME		NS16550_80800_LABEL
+
+#define L2_SRAM_BASE				CONFIG_SRAM_BASE_ADDRESS
+
+#define L2_SRAM_SIZE				CONFIG_SRAM_SIZE_0 * 1024
+
+/* End of SoC Level DTS fixup file */
diff --git a/arch/xtensa/soc/intel_s1000/linker.ld b/arch/xtensa/soc/intel_s1000/linker.ld
index fce9c1ffddc..1b836653c74 100644
--- a/arch/xtensa/soc/intel_s1000/linker.ld
+++ b/arch/xtensa/soc/intel_s1000/linker.ld
@@ -15,6 +15,7 @@ OUTPUT_ARCH(xtensa)
 #define _LINKER
 #define _ASMLANGUAGE
 
+#include <generated_dts_board.h>
 #include "memory.h"
 #include <autoconf.h>
 #include <linker/sections.h>
diff --git a/arch/xtensa/soc/intel_s1000/memory.h b/arch/xtensa/soc/intel_s1000/memory.h
index c98dd08425f..2373698a6e9 100644
--- a/arch/xtensa/soc/intel_s1000/memory.h
+++ b/arch/xtensa/soc/intel_s1000/memory.h
@@ -7,8 +7,6 @@
 #define __INC_MEMORY_H
 
 /* L2 HP SRAM */
-#define L2_SRAM_BASE				0xBE000000
-#define L2_SRAM_SIZE				0x00300000
 #define L2_VECTOR_SIZE				0x1000
 
 /* The reset vector address in SRAM and its size */
diff --git a/boards/xtensa/intel_s1000_crb/Kconfig.board b/boards/xtensa/intel_s1000_crb/Kconfig.board
index 16b3b2f33d6..00b86df4544 100644
--- a/boards/xtensa/intel_s1000_crb/Kconfig.board
+++ b/boards/xtensa/intel_s1000_crb/Kconfig.board
@@ -6,3 +6,4 @@
 config  BOARD_INTEL_S1000_CRB
 	bool "Xtensa on Intel_S1000"
 	depends on SOC_INTEL_S1000
+	select HAS_DTS
diff --git a/boards/xtensa/intel_s1000_crb/Kconfig.defconfig b/boards/xtensa/intel_s1000_crb/Kconfig.defconfig
index f89602cda5c..7ad0763fc1d 100644
--- a/boards/xtensa/intel_s1000_crb/Kconfig.defconfig
+++ b/boards/xtensa/intel_s1000_crb/Kconfig.defconfig
@@ -82,10 +82,6 @@ config UART_NS16550_PORT_0
 
 if UART_NS16550_PORT_0
 
-config UART_NS16550_PORT_0_NAME
-	default "UART_0"
-config UART_NS16550_PORT_0_BAUD_RATE
-	default 115200
 config UART_NS16550_PORT_0_OPTIONS
 	default 0
 config UART_INTERRUPT_DRIVEN
diff --git a/boards/xtensa/intel_s1000_crb/intel_s1000_crb.dts b/boards/xtensa/intel_s1000_crb/intel_s1000_crb.dts
new file mode 100644
index 00000000000..6c77184aff1
--- /dev/null
+++ b/boards/xtensa/intel_s1000_crb/intel_s1000_crb.dts
@@ -0,0 +1,23 @@
+/dts-v1/;
+
+#include "intel_s1000.dtsi"
+
+/ {
+	model = "intel_s1000_crb";
+	compatible = "intel,s1000";
+
+	aliases {
+		uart_0 = &uart0;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart0;
+	};
+};
+
+&uart0 {
+	status = "ok";
+	current-speed = <115200>;
+};
+
diff --git a/dts/xtensa/intel_s1000.dtsi b/dts/xtensa/intel_s1000.dtsi
new file mode 100644
index 00000000000..ef485f5add1
--- /dev/null
+++ b/dts/xtensa/intel_s1000.dtsi
@@ -0,0 +1,44 @@
+#include "skeleton.dtsi"
+
+#define __SIZE_K(x) (x * 1024)
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "LX6";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "LX6";
+			reg = <1>;
+		};
+
+	};
+
+	sram0: memory@0xbe000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0xbe000000 0x300000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		uart0: uart@80800 {
+			compatible = "ns16550";
+			reg = <0x80800 0x400>;
+			label = "UART_0";
+
+			status = "disabled";
+		};
+	};
+};
diff --git a/include/arch/xtensa/arch.h b/include/arch/xtensa/arch.h
index 84704c7983b..2f718ceb4e8 100644
--- a/include/arch/xtensa/arch.h
+++ b/include/arch/xtensa/arch.h
@@ -19,6 +19,7 @@
 extern "C" {
 #endif
 
+#include <generated_dts_board.h>
 #if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
 #include "sys_io.h" /* Include from the very same folder of this file */
 #include <zephyr/types.h>