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linker: xtensa: move IDT_LIST region

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Move the IDT_LIST memory region to the location recommended by
`intlist.ld`. The documentation specifies that this region should not
overlap other regions, and there is no guarantee that the area after the
`SRAM` region is not used. The end of the address space is much less
likely to be a valid RAM address.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This commit is contained in:
Jordan Yates 2021-06-13 10:52:22 +10:00 • committed by Anas Nashif
commit 9505ee89a3
5 changed files with 5 additions and 5 deletions
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2
soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
View file

@ -87,7 +87,7 @@
* Interrupt Descriptor Table (IDT). This is a bogus address as this * Interrupt Descriptor Table (IDT). This is a bogus address as this
* section will be stripped off in the final image. * section will be stripped off in the final image.
*/ */
#define IDT_BASE (RAM_BASE + RAM_SIZE) #define IDT_BASE 0xFFFFDFFF
/* size of the Interrupt Descriptor Table (IDT) */ /* size of the Interrupt Descriptor Table (IDT) */
#define IDT_SIZE 0x2000 #define IDT_SIZE 0x2000

2
soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
View file

@ -84,7 +84,7 @@
* Interrupt Descriptor Table (IDT). This is a bogus address as this * Interrupt Descriptor Table (IDT). This is a bogus address as this
* section will be stripped off in the final image. * section will be stripped off in the final image.
*/ */
#define IDT_BASE (RAM_BASE + RAM_SIZE) #define IDT_BASE 0xFFFFDFFF
/* size of the Interrupt Descriptor Table (IDT) */ /* size of the Interrupt Descriptor Table (IDT) */
#define IDT_SIZE 0x2000 #define IDT_SIZE 0x2000

2
soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
View file

@ -84,7 +84,7 @@
* Interrupt Descriptor Table (IDT). This is a bogus address as this * Interrupt Descriptor Table (IDT). This is a bogus address as this
* section will be stripped off in the final image. * section will be stripped off in the final image.
*/ */
#define IDT_BASE (RAM_BASE + RAM_SIZE) #define IDT_BASE 0xFFFFDFFF
/* size of the Interrupt Descriptor Table (IDT) */ /* size of the Interrupt Descriptor Table (IDT) */
#define IDT_SIZE 0x2000 #define IDT_SIZE 0x2000

2
soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
View file

@ -84,7 +84,7 @@
* Interrupt Descriptor Table (IDT). This is a bogus address as this * Interrupt Descriptor Table (IDT). This is a bogus address as this
* section will be stripped off in the final image. * section will be stripped off in the final image.
*/ */
#define IDT_BASE (RAM_BASE + RAM_SIZE) #define IDT_BASE 0xFFFFDFFF
/* size of the Interrupt Descriptor Table (IDT) */ /* size of the Interrupt Descriptor Table (IDT) */
#define IDT_SIZE 0x2000 #define IDT_SIZE 0x2000

2
soc/xtensa/intel_s1000/memory.h
View file

@ -63,7 +63,7 @@
* Interrupt Descriptor Table (IDT). This is a bogus address as this * Interrupt Descriptor Table (IDT). This is a bogus address as this
* section will be stripped off in the final image. * section will be stripped off in the final image.
*/ */
#define IDT_BASE (RAM_BASE + RAM_SIZE) #define IDT_BASE 0xFFFFDFFF
/* size of the Interrupt Descriptor Table (IDT) */ /* size of the Interrupt Descriptor Table (IDT) */
#define IDT_SIZE 0x2000 #define IDT_SIZE 0x2000