From 9505ee89a3401af93ffddc68e7b04fc948e2f89a Mon Sep 17 00:00:00 2001 From: Jordan Yates Date: Sun, 13 Jun 2021 10:52:22 +1000 Subject: [PATCH] linker: xtensa: move IDT_LIST region Move the IDT_LIST memory region to the location recommended by `intlist.ld`. The documentation specifies that this region should not overlap other regions, and there is no guarantee that the area after the `SRAM` region is not used. The end of the address space is much less likely to be a valid RAM address. Signed-off-by: Jordan Yates --- soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h | 2 +- soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h | 2 +- soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h | 2 +- soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h | 2 +- soc/xtensa/intel_s1000/memory.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h index 37f54ed131f..3e3fa833c9d 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h @@ -87,7 +87,7 @@ * Interrupt Descriptor Table (IDT). This is a bogus address as this * section will be stripped off in the final image. */ -#define IDT_BASE (RAM_BASE + RAM_SIZE) +#define IDT_BASE 0xFFFFDFFF /* size of the Interrupt Descriptor Table (IDT) */ #define IDT_SIZE 0x2000 diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index ab8302d1fc3..6ffe7d4d4d9 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -84,7 +84,7 @@ * Interrupt Descriptor Table (IDT). This is a bogus address as this * section will be stripped off in the final image. */ -#define IDT_BASE (RAM_BASE + RAM_SIZE) +#define IDT_BASE 0xFFFFDFFF /* size of the Interrupt Descriptor Table (IDT) */ #define IDT_SIZE 0x2000 diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index 0ffcebc39ba..27aac28fda1 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -84,7 +84,7 @@ * Interrupt Descriptor Table (IDT). This is a bogus address as this * section will be stripped off in the final image. */ -#define IDT_BASE (RAM_BASE + RAM_SIZE) +#define IDT_BASE 0xFFFFDFFF /* size of the Interrupt Descriptor Table (IDT) */ #define IDT_SIZE 0x2000 diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index 7751ef6078a..ddfbe8b0603 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -84,7 +84,7 @@ * Interrupt Descriptor Table (IDT). This is a bogus address as this * section will be stripped off in the final image. */ -#define IDT_BASE (RAM_BASE + RAM_SIZE) +#define IDT_BASE 0xFFFFDFFF /* size of the Interrupt Descriptor Table (IDT) */ #define IDT_SIZE 0x2000 diff --git a/soc/xtensa/intel_s1000/memory.h b/soc/xtensa/intel_s1000/memory.h index 1e6b9147bfd..1995bf217c2 100644 --- a/soc/xtensa/intel_s1000/memory.h +++ b/soc/xtensa/intel_s1000/memory.h @@ -63,7 +63,7 @@ * Interrupt Descriptor Table (IDT). This is a bogus address as this * section will be stripped off in the final image. */ -#define IDT_BASE (RAM_BASE + RAM_SIZE) +#define IDT_BASE 0xFFFFDFFF /* size of the Interrupt Descriptor Table (IDT) */ #define IDT_SIZE 0x2000