dts: Add cpus and cpu nodes missing properties

This patch adds #address-cell, #size-cell properties to
cpus container node and device_type, reg properties to
cpu node.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>

dts/arm/atmel/sam3x.dtsi

@@ -8,8 +8,13 @@
 
 / {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-m4";
+			reg = <0>;
 		};
 	};
 

dts/arm/atmel/sam4s.dtsi

@@ -8,8 +8,13 @@
 
 / {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-m4";
+			reg = <0>;
 		};
 	};
 

dts/arm/atmel/same70.dtsi

@@ -10,8 +10,13 @@
 
 / {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-m7";
+			reg = <0>;
 		};
 	};
 

dts/arm/nordic/nrf51822.dtsi

@@ -3,8 +3,13 @@
 
 / {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-m0";
+			reg = <0>;
 		};
 	};
 

dts/arm/nordic/nrf52832.dtsi

@@ -3,8 +3,13 @@
 
 / {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-m4f";
+			reg = <0>;
 		};
 	};
 

dts/arm/nordic/nrf52840.dtsi

@@ -3,8 +3,13 @@
 
 / {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-m4f";
+			reg = <0>;
 		};
 	};
 

dts/arm/nxp/nxp_k6x.dtsi

@@ -2,8 +2,13 @@
 
 / {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-m4f";
+			reg = <0>;
 		};
 	};
 

dts/arm/nxp/nxp_kl25z.dtsi

@@ -2,8 +2,13 @@
 
 / {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-m0+";
+			reg = <0>;
 		};
 	};
 

dts/arm/nxp/nxp_kw40z.dtsi

@@ -2,8 +2,13 @@
 
 / {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-m0+";
+			reg = <0>;
 		};
 	};
 

dts/arm/nxp/nxp_kw41z.dtsi

@@ -2,8 +2,13 @@
 
 / {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-m0+";
+			reg = <0>;
 		};
 	};
 

dts/arm/st/stm32f103Xb.dtsi

@@ -11,6 +11,17 @@
 #include <st/mem.h>
 
 / {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m3";
+			reg = <0>;
+		};
+	};
+
 	flash0: flash {
 		reg = <0x08000000 DT_FLASH_SIZE>;
 	};

dts/arm/st/stm32f103Xe.dtsi

@@ -11,6 +11,17 @@
 #include <st/mem.h>
 
 / {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m3";
+			reg = <0>;
+		};
+	};
+
 	flash0: flash {
 		reg = <0x08000000 DT_FLASH_SIZE>;
 	};

dts/arm/st/stm32f107.dtsi

@@ -8,6 +8,17 @@
 #include <st/mem.h>
 
 / {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m3";
+			reg = <0>;
+		};
+	};
+
 	flash0: flash {
 		reg = <0x08000000 DT_FLASH_SIZE>;
 	};

dts/arm/st/stm32f303.dtsi

@@ -8,6 +8,17 @@
 #include <st/mem.h>
 
 / {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
 	flash0: flash {
 		reg = <0x08000000 DT_FLASH_SIZE>;
 	};

dts/arm/st/stm32f334.dtsi

@@ -8,6 +8,17 @@
 #include <st/mem.h>
 
 / {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
 	flash0: flash {
 		reg = <0x08000000 DT_FLASH_SIZE>;
 	};

dts/arm/st/stm32f373.dtsi

@@ -8,6 +8,17 @@
 #include <st/mem.h>
 
 / {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
 	flash0: flash {
 		reg = <0x08000000 DT_FLASH_SIZE>;
 	};

dts/arm/st/stm32f4.dtsi

@@ -8,6 +8,17 @@
 #include <st/mem.h>
 
 / {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
 	flash0: flash {
 		reg = <0x08000000 DT_FLASH_SIZE>;
 	};

dts/arm/st/stm32l432.dtsi

@@ -8,6 +8,17 @@
 #include <st/mem.h>
 
 / {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
 	flash0: flash {
 		reg = <0x08000000 DT_FLASH_SIZE>;
 	};

dts/arm/st/stm32l475.dtsi

@@ -8,6 +8,17 @@
 #include <st/mem.h>
 
 / {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
 	flash0: flash {
 		reg = <0x08000000 DT_FLASH_SIZE>;
 	};

dts/arm/ti/cc2650.dtsi

@@ -7,10 +7,14 @@
 #include "armv7-m.dtsi"
 
 / {
-	soc {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-m3";
+			reg = <0>;
 		};
 	};
 
@@ -24,6 +28,7 @@
 		reg = <0x0 0x20000>;
 	};
 
+	soc {
 		gpioa: gpio@40022000 {
 			compatible = "ti,cc2650-gpio";
 			reg = <0x40022000 0xE4>;

dts/arm/ti/cc32xx.dtsi

@@ -9,8 +9,13 @@
 
 / {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-m4";
+			reg = <0>;
 		};
 	};
 

dts/arm/ti/lm3s6965.dtsi

@@ -2,8 +2,13 @@
 
 / {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-m3";
+			reg = <0>;
 		};
 	};
 

dts/x86/intel_curie.dtsi

@@ -3,12 +3,19 @@
 
 / {
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "intel,quark";
+			reg = <0>;
 		};
 
 		cpu@1 {
+			device_type = "cpu";
 			compatible = "arc";
+			reg = <1>;
 		};
 	};