boards: st: add the nucleo_wba65ri board
Introduce the stm32WBA56 nucleo board. HSE32 divided by 2 is the source clock. Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu
Benjamin Cabé
parent
95728178f5
commit
940993cc4b
11 changed files with 547 additions and 0 deletions
13
boards/st/nucleo_wba65ri/Kconfig.defconfig
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13
boards/st/nucleo_wba65ri/Kconfig.defconfig
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# STM32WBA65RI Nucleo board configuration
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# Copyright (c) 2025 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_NUCLEO_WBA65RI
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config SPI_STM32_INTERRUPT
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default y
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depends on SPI
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endif # BOARD_NUCLEO_WBA65RI
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5
boards/st/nucleo_wba65ri/Kconfig.nucleo_wba65ri
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5
boards/st/nucleo_wba65ri/Kconfig.nucleo_wba65ri
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# Copyright (c) 2025 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_NUCLEO_WBA65RI
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select SOC_STM32WBA65XX
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39
boards/st/nucleo_wba65ri/arduino_r3_connector.dtsi
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boards/st/nucleo_wba65ri/arduino_r3_connector.dtsi
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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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arduino_header: connector {
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compatible = "arduino-header-r3";
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#gpio-cells = <2>;
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gpio-map-mask = <0xffffffff 0xffffffc0>;
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gpio-map-pass-thru = <0 0x3f>;
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gpio-map = <0 0 &gpioa 4 0>, /* A0 */
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<1 0 &gpioa 6 0>, /* A1 */
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<2 0 &gpioa 2 0>, /* A2 */
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<3 0 &gpioa 1 0>, /* A3 */
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<4 0 &gpioa 5 0>, /* A4 */
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<5 0 &gpioa 0 0>, /* A5 */
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<6 0 &gpioa 11 0>, /* D0 */
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<7 0 &gpioa 12 0>, /* D1 */
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<8 0 &gpioe 0 0>, /* D2 */
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<9 0 &gpiob 13 0>, /* D3 */
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<10 0 &gpioa 3 0>, /* D4 */
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<11 0 &gpiob 14 0>, /* D5 */
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<12 0 &gpiob 0 0>, /* D6 */
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<13 0 &gpiod 14 0>, /* D7 */
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<14 0 &gpioa 10 0>, /* D8 */
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<15 0 &gpiob 11 0>, /* D9 */
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<16 0 &gpiob 9 0>, /* D10 */
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<17 0 &gpioc 3 0>, /* D11 */
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<18 0 &gpioa 9 0>, /* D12 */
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<19 0 &gpiob 10 0>, /* D13 */
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<20 0 &gpiob 1 0>, /* D14 */
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<21 0 &gpiob 2 0>; /* D15 */
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};
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};
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arduino_i2c: &i2c1 {};
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arduino_spi: &spi1 {};
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6
boards/st/nucleo_wba65ri/board.cmake
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6
boards/st/nucleo_wba65ri/board.cmake
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
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include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
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6
boards/st/nucleo_wba65ri/board.yml
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boards/st/nucleo_wba65ri/board.yml
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board:
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name: nucleo_wba65ri
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full_name: Nucleo WBA65RI
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vendor: st
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socs:
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- name: stm32wba65xx
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BIN
boards/st/nucleo_wba65ri/doc/img/nucleo_wba65ri.webp
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BIN
boards/st/nucleo_wba65ri/doc/img/nucleo_wba65ri.webp
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Binary file not shown.
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After Width: | Height: | Size: 64 KiB |
241
boards/st/nucleo_wba65ri/doc/nucleo_wba65ri.rst
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boards/st/nucleo_wba65ri/doc/nucleo_wba65ri.rst
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.. zephyr:board:: nucleo_wba65ri
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Overview
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********
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NUCLEO-WBA65RI is a Bluetooth® Low Energy, 802.15.4 and Zigbee® wireless
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and ultra-low-power board embedding a powerful and ultra-low-power radio
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compliant with the Bluetooth® Low Energy SIG specification v5.4
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with IEEE 802.15.4-2015 and Zigbee® specifications.
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The ARDUINO® Uno V3 connectivity support and the ST morpho headers allow the
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easy expansion of the functionality of the STM32 Nucleo open development
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platform with a wide choice of specialized shields.
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- Ultra-low-power wireless STM32WBA65RI microcontroller based on the Arm®
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Cortex®‑M33 core, featuring 2 Mbyte of flash memory and 512 Kbytes of SRAM in
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a VFQFPN68 package
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- MCU RF board (MB2130):
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- 2.4 GHz RF transceiver supporting Bluetooth® specification v5.4
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- Arm® Cortex® M33 CPU with TrustZone®, MPU, DSP, and FPU
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- Integrated PCB antenna
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- Three user LEDs
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- Three user and one reset push-buttons
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- Board connectors:
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- 2 USB Type-C
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- ARDUINO® Uno V3 expansion connector
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- ST morpho headers for full access to all STM32 I/Os
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- Flexible power-supply options: ST-LINK USB VBUS or external sources
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- On-board STLINK-V3MODS debugger/programmer with USB re-enumeration capability:
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mass storage, Virtual COM port, and debug port
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Hardware
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********
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The STM32WBA65xx multiprotocol wireless and ultralow power devices embed a
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powerful and ultralow power radio compliant with the Bluetooth® SIG Low Energy
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specification 5.4. They contain a high-performance Arm Cortex-M33 32-bit RISC
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core. They operate at a frequency of up to 100 MHz.
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- Includes ST state-of-the-art patented technology
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- Ultra low power radio:
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- 2.4 GHz radio
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- RF transceiver supporting Bluetooth® Low Energy 5.4 specification
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IEEE 802.15.4-2015 PHY and MAC, supporting Thread, Matter and Zigbee®
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- Proprietary protocols
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- RX sensitivity: -96 dBm (Bluetooth® Low Energy at 1 Mbps)
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and -100 dBm (IEEE 802.15.4 at 250 kbps)
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- Programmable output power, up to +10 dBm with 1 dB steps
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- Support for external PA
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- Integrated balun to reduce BOM
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- Suitable for systems requiring compliance with radio frequency regulations
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ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66
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- Ultra low power platform with FlexPowerControl:
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- 1.71 to 3.6 V power supply
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- - 40 °C to 85 °C temperature range
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- Autonomous peripherals with DMA, functional down to Stop 1 mode
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- TBD nA Standby mode (16 wake-up pins)
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- TBD nA Standby mode with RTC
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- TBD µA Standby mode with 64 KB SRAM
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- TBD µA Stop 2 mode with 64 KB SRAM
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- TBD µA/MHz Run mode at 3.3 V
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- Radio: Rx TBD mA / Tx at 0 dBm TBD mA
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- Core: Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU
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- ART Accelerator™: 8-Kbyte instruction cache allowing 0-wait-state execution
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from flash memory (frequency up to 100 MHz, 150 DMIPS)
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- Power management: embedded regulator LDO and SMPS step-down converter
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- Supporting switch on-the-fly and voltage scaling
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- Benchmarks:
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- 1.5 DMIPS/MHz (Drystone 2.1)
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- 410 CoreMark® (4.10 CoreMark/MHz)
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- Clock sources:
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- 32 MHz crystal oscillator
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- 32 kHz crystal oscillator (LSE)
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- Internal low-power 32 kHz (±5%) RC
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- Internal 16 MHz factory trimmed RC (±1%)
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- PLL for system clock and ADC
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- Memories:
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- 2 MB flash memory with ECC, including 256 Kbytes with 100 cycles
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- 512 KB SRAM, including 64 KB with parity check
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- 512-byte (32 rows) OTP
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- Rich analog peripherals (independent supply):
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- 12-bit ADC 2.5 Msps with hardware oversampling
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- Communication peripherals:
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- Four UARTs (ISO 7816, IrDA, modem)
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- Three SPIs
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- Four I2C Fm+ (1 Mbit/s), SMBus/PMBus®
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- System peripherals:
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- Touch sensing controller, up to 24 sensors, supporting touch key, linear,
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rotary touch sensors
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- One 16-bit, advanced motor control timer
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- Three 16-bit timers
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- Two 32-bit timer
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- Two low-power 16-bit timers (available in Stop mode)
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- Two Systick timers
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- RTC with hardware calendar and calibration
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- Two watchdogs
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- 8-channel DMA controller, functional in Stop mode
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- Security and cryptography:
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- Arm® TrustZone® and securable I/Os, memories, and peripherals
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- Flexible life cycle scheme with RDP and password protected debug
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- Root of trust thanks to unique boot entry and secure hide protection area (HDP)
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- SFI (secure firmware installation) thanks to embedded RSS (root secure services)
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- Secure data storage with root hardware unique key (RHUK)
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- Secure firmware upgrade support with TF-M
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- Two AES co-processors, including one with DPA resistance
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- Public key accelerator, DPA resistant
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- HASH hardware accelerator
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- True random number generator, NIST SP800-90B compliant
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- 96-bit unique ID
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- Active tampers
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- CRC calculation unit
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- Up to 86 I/Os (most of them 5 V-tolerant) with interrupt capability
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- Development support:
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- Serial wire debug (SWD), JTAG
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- ECOPACK2 compliant package
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More information about STM32WBA series can be found here:
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- `STM32WBA Series on www.st.com`_
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Connections and IOs
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===================
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Nucleo WBA65RI Board has 4 GPIO controllers. These controllers are responsible for pin muxing,
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input/output, pull-up, etc.
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Default Zephyr Peripheral Mapping:
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----------------------------------
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.. rst-class:: rst-columns
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- USART_1 TX/RX : PB12/PA8
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- I2C_1_SCL : PB2
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- I2C_1_SDA : PB1
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- USER_PB : PC13
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- LD1 : PD8
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- SPI_1_NSS : PA12 (arduino_spi)
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- SPI_1_SCK : PB4 (arduino_spi)
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- SPI_1_MISO : PB3 (arduino_spi)
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- SPI_1_MOSI : PA15 (arduino_spi)
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System Clock
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------------
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Nucleo WBA65RI System Clock could be driven by internal or external oscillator,
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as well as main PLL clock. By default System clock is driven by HSE+PLL clock at 100MHz.
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Serial Port
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-----------
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Nucleo WBA65RI board has 3 U(S)ARTs. The Zephyr console output is assigned to USART1.
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Default settings are 115200 8N1.
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Programming and Debugging
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*************************
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.. zephyr:board-supported-runners::
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Nucleo WBA65RI board includes an ST-LINK/V3 embedded debug tool interface.
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It could be used for flash and debug using either OpenOCD or STM32Cube ecosystem tools.
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Flashing
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========
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The board is configured to be flashed using west `STM32CubeProgrammer`_ runner,
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so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required.
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Alternatively, openocd can also be used to flash the board using
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the ``--runner`` (or ``-r``) option:
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.. code-block:: console
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$ west flash --runner openocd
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Flashing an application to Nucleo WBA65RI
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-----------------------------------------
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Here is an example for the :zephyr:code-sample:`blinky` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/basic/blinky
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:board: nucleo_wba65ri
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:goals: build flash
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You will see the LED blinking every second.
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Debugging
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=========
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Debugging using OpenOCD
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-----------------------
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You can debug an application in the usual way using OpenOCD. Here is an example for the
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:zephyr:code-sample:`blinky` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/basic/blinky
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:board: nucleo_wba65ri
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:maybe-skip-config:
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:goals: debug
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.. _STM32WBA Series on www.st.com:
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https://www.st.com/en/microcontrollers-microprocessors/stm32wba-series.html
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.. _STM32CubeProgrammer:
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https://www.st.com/en/development-tools/stm32cubeprog.html
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168
boards/st/nucleo_wba65ri/nucleo_wba65ri.dts
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168
boards/st/nucleo_wba65ri/nucleo_wba65ri.dts
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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <st/wba/stm32wba65Xi.dtsi>
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#include <st/wba/stm32wba65rivx-pinctrl.dtsi>
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#include "arduino_r3_connector.dtsi"
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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/ {
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model = "STMicroelectronics STM32WBA65RI-NUCLEO board";
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compatible = "st,stm32wba65ri-nucleo";
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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zephyr,bt-c2h-uart = &usart1;
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zephyr,console = &usart1;
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zephyr,shell-uart = &usart1;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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};
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leds: leds {
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compatible = "gpio-leds";
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blue_led_1: led_0 {
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gpios = <&gpiod 8 GPIO_ACTIVE_LOW>;
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label = "User LD1";
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};
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green_led_2: led_1 {
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gpios = <&gpioc 4 GPIO_ACTIVE_LOW>;
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label = "User LD2";
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};
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red_led_3: led_2 {
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gpios = <&gpiob 8 GPIO_ACTIVE_LOW>;
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label = "User LD3";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button_1: button_0 {
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label = "User B1";
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gpios = <&gpioc 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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zephyr,code = <INPUT_KEY_0>;
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};
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user_button_2: button_1 {
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label = "User B2";
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gpios = <&gpioc 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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zephyr,code = <INPUT_KEY_1>;
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};
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user_button_3: button_2 {
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label = "User B3";
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gpios = <&gpiob 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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zephyr,code = <INPUT_KEY_2>;
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};
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};
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aliases {
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led0 = &blue_led_1;
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led1 = &green_led_2;
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led2 = &red_led_3;
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sw0 = &user_button_1;
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sw1 = &user_button_2;
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sw2 = &user_button_3;
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mcuboot-led0 = &blue_led_1;
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mcuboot-button0 = &user_button_1;
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};
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};
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&clk_lse {
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status = "okay";
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};
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&clk_hse {
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hse-div2;
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status = "okay";
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};
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&clk_hsi {
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status = "okay";
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};
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&rcc {
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clocks = <&clk_hse>;
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clock-frequency = <DT_FREQ_M(16)>;
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ahb-prescaler = <1>;
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ahb5-prescaler = <2>;
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apb1-prescaler = <1>;
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apb2-prescaler = <2>;
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apb7-prescaler = <1>;
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};
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&iwdg {
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status = "okay";
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};
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&rtc {
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status = "okay";
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clocks = <&rcc STM32_CLOCK(APB7, 21)>,
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<&rcc STM32_SRC_LSE RTC_SEL(1)>;
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prescaler = <32768>;
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};
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&usart1 {
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clocks = <&rcc STM32_CLOCK(APB2, 14)>,
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<&rcc STM32_SRC_HSI16 USART1_SEL(2)>;
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pinctrl-0 = <&usart1_tx_pb12 &usart1_rx_pa8>;
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pinctrl-1 = <&analog_pb12 &analog_pa8>;
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pinctrl-names = "default", "sleep";
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current-speed = <115200>;
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status = "okay";
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};
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&spi1 {
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pinctrl-0 = <&spi1_nss_pa12 &spi1_sck_pb4
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&spi1_miso_pb3 &spi1_mosi_pa15>;
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pinctrl-names = "default";
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status = "okay";
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};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_scl_pb2 &i2c1_sda_pb1>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
clock-frequency = <I2C_BITRATE_FAST>;
|
||||
};
|
||||
|
||||
&adc4 {
|
||||
pinctrl-0 = <&adc4_in8_pa1>;
|
||||
pinctrl-names = "default";
|
||||
st,adc-clock-source = "ASYNC";
|
||||
st,adc-prescaler = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
stm32_lp_tick_source: &lptim1 {
|
||||
clocks = <&rcc STM32_CLOCK(APB7, 11)>,
|
||||
<&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
storage_partition: partition@1c0000 {
|
||||
label = "storage";
|
||||
reg = <0x001c0000 DT_SIZE_K(256)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
19
boards/st/nucleo_wba65ri/nucleo_wba65ri.yaml
Normal file
19
boards/st/nucleo_wba65ri/nucleo_wba65ri.yaml
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
identifier: nucleo_wba65ri
|
||||
name: ST Nucleo WBA65RI
|
||||
type: mcu
|
||||
arch: arm
|
||||
toolchain:
|
||||
- zephyr
|
||||
- gnuarmemb
|
||||
supported:
|
||||
- gpio
|
||||
- i2c
|
||||
- spi
|
||||
- adc
|
||||
- rng
|
||||
- arduino_gpio
|
||||
- arduino_i2c
|
||||
- arduino_spi
|
||||
ram: 512
|
||||
flash: 2048
|
||||
vendor: st
|
||||
24
boards/st/nucleo_wba65ri/nucleo_wba65ri_defconfig
Normal file
24
boards/st/nucleo_wba65ri/nucleo_wba65ri_defconfig
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
# Copyright (c) 2025 STMicroelectronics
|
||||
|
||||
# Enable UART driver
|
||||
CONFIG_SERIAL=y
|
||||
|
||||
# Enable GPIO
|
||||
CONFIG_GPIO=y
|
||||
|
||||
# Enable clock
|
||||
CONFIG_CLOCK_CONTROL=y
|
||||
|
||||
# Console
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
|
||||
# Enable MPU
|
||||
CONFIG_ARM_MPU=y
|
||||
|
||||
# Enable HW stack protection
|
||||
CONFIG_HW_STACK_PROTECTION=y
|
||||
|
||||
# Enable the internal SMPS regulator
|
||||
CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
|
||||
26
boards/st/nucleo_wba65ri/support/openocd.cfg
Normal file
26
boards/st/nucleo_wba65ri/support/openocd.cfg
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
# Note: Using OpenOCD using nucleo_wba65ri requires using openocd fork.
|
||||
# See board documentation for more information
|
||||
|
||||
source [find interface/stlink-dap.cfg]
|
||||
|
||||
set WORKAREASIZE 0x8000
|
||||
|
||||
transport select "dapdirect_swd"
|
||||
|
||||
# Enable debug when in low power modes
|
||||
set ENABLE_LOW_POWER 1
|
||||
|
||||
# Stop Watchdog counters when halt
|
||||
set STOP_WATCHDOG 1
|
||||
|
||||
# STlink Debug clock frequency
|
||||
set CLOCK_FREQ 8000
|
||||
|
||||
# Reset configuration
|
||||
# use hardware reset, connect under reset
|
||||
# connect_assert_srst needed if low power mode application running (WFI...)
|
||||
reset_config srst_only srst_nogate
|
||||
|
||||
source [find target/stm32wbax.cfg]
|
||||
|
||||
gdb_memory_map disable
|
||||
Loading…
Add table
Add a link
Reference in a new issue