drivers: can: add NXP LPC MCAN front-end for the Bosch MCAN driver
Add a NXP LPC MCAN-specific front-end for the generic Bosch MCAN driver. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit is contained in:
Henrik Brix Andersen
Carles Cufí
parent
78075457ba
commit
93c6b7413b
6 changed files with 319 additions and 7 deletions
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@ -1,6 +1,7 @@
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# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_sources_ifdef(CONFIG_CAN_MCUX_MCAN can_mcux_mcan.c)
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zephyr_library_sources_ifdef(CONFIG_CAN can_common.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_LOOPBACK can_loopback.c)
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@ -18,3 +18,10 @@ config CAN_MAX_FILTER
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range 1 64 if SOC_SERIES_IMX_RT
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help
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Defines maximum number of concurrent active RX filters
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config CAN_MCUX_MCAN
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bool "MCUX MCAN driver"
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depends on HAS_MCUX_MCAN && CLOCK_CONTROL
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select CAN_MCAN
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help
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Enable support for mcux mcan driver.
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@ -297,6 +297,24 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg,
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(can->crel & CAN_MCAN_CREL_DAY) >> CAN_MCAN_CREL_DAY_POS);
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#ifndef CONFIG_CAN_STM32FD
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#ifdef CONFIG_CAN_MCUX_MCAN
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uint32_t mrba = (uint32_t)msg_ram & CAN_MCAN_MRBA_BA_MSK;
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can->mrba = mrba;
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can->sidfc = (((uint32_t)msg_ram->std_filt - mrba) & CAN_MCAN_SIDFC_FLSSA_MSK) |
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(ARRAY_SIZE(msg_ram->std_filt) << CAN_MCAN_SIDFC_LSS_POS);
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can->xidfc = (((uint32_t)msg_ram->ext_filt - mrba) & CAN_MCAN_XIDFC_FLESA_MSK) |
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(ARRAY_SIZE(msg_ram->ext_filt) << CAN_MCAN_XIDFC_LSS_POS);
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can->rxf0c = (((uint32_t)msg_ram->rx_fifo0 - mrba) & CAN_MCAN_RXF0C_F0SA) |
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(ARRAY_SIZE(msg_ram->rx_fifo0) << CAN_MCAN_RXF0C_F0S_POS);
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can->rxf1c = (((uint32_t)msg_ram->rx_fifo1 - mrba) & CAN_MCAN_RXF1C_F1SA) |
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(ARRAY_SIZE(msg_ram->rx_fifo1) << CAN_MCAN_RXF1C_F1S_POS);
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can->rxbc = (((uint32_t)msg_ram->rx_buffer - mrba) & CAN_MCAN_RXBC_RBSA);
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can->txefc = (((uint32_t)msg_ram->tx_event_fifo - mrba) & CAN_MCAN_TXEFC_EFSA_MSK) |
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(ARRAY_SIZE(msg_ram->tx_event_fifo) << CAN_MCAN_TXEFC_EFS_POS);
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can->txbc = (((uint32_t)msg_ram->tx_buffer - mrba) & CAN_MCAN_TXBC_TBSA_MSK) |
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(ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS);
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#else /* CONFIG_CAN_MCUX_MCAN */
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can->sidfc = ((uint32_t)msg_ram->std_filt & CAN_MCAN_SIDFC_FLSSA_MSK) |
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(ARRAY_SIZE(msg_ram->std_filt) << CAN_MCAN_SIDFC_LSS_POS);
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can->xidfc = ((uint32_t)msg_ram->ext_filt & CAN_MCAN_XIDFC_FLESA_MSK) |
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@ -311,6 +329,8 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg,
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CAN_MCAN_TXEFC_EFS_POS);
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can->txbc = ((uint32_t)msg_ram->tx_buffer & CAN_MCAN_TXBC_TBSA) |
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(ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS);
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#endif /* !CONFIG_CAN_MCUX_MCAN */
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if (sizeof(msg_ram->tx_buffer[0].data) <= 24) {
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can->txesc = (sizeof(msg_ram->tx_buffer[0].data) - 8) / 4;
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} else {
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@ -8,14 +8,20 @@
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#ifndef ZEPHYR_DRIVERS_CAN_MCAN_H_
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#define ZEPHYR_DRIVERS_CAN_MCAN_H_
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#define NUM_STD_FILTER_ELEMENTS DT_PROP(DT_PATH(soc, can), std_filter_elements)
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#define NUM_EXT_FILTER_ELEMENTS DT_PROP(DT_PATH(soc, can), ext_filter_elements)
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#define NUM_RX_FIFO0_ELEMENTS DT_PROP(DT_PATH(soc, can), rx_fifo0_elements)
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#define NUM_RX_FIFO1_ELEMENTS DT_PROP(DT_PATH(soc, can), rx_fifo0_elements)
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#define NUM_RX_BUF_ELEMENTS DT_PROP(DT_PATH(soc, can), rx_buffer_elements)
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#ifdef CONFIG_CAN_MCUX_MCAN
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#define MCAN_DT_PATH DT_NODELABEL(can0)
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#else
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#define MCAN_DT_PATH DT_PATH(soc, can)
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#endif
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#define NUM_STD_FILTER_ELEMENTS DT_PROP(MCAN_DT_PATH, std_filter_elements)
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#define NUM_EXT_FILTER_ELEMENTS DT_PROP(MCAN_DT_PATH, ext_filter_elements)
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#define NUM_RX_FIFO0_ELEMENTS DT_PROP(MCAN_DT_PATH, rx_fifo0_elements)
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#define NUM_RX_FIFO1_ELEMENTS DT_PROP(MCAN_DT_PATH, rx_fifo0_elements)
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#define NUM_RX_BUF_ELEMENTS DT_PROP(MCAN_DT_PATH, rx_buffer_elements)
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#define NUM_TX_EVENT_FIFO_ELEMENTS \
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DT_PROP(DT_PATH(soc, can), tx_event_fifo_elements)
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#define NUM_TX_BUF_ELEMENTS DT_PROP(DT_PATH(soc, can), tx_buffer_elements)
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DT_PROP(MCAN_DT_PATH, tx_event_fifo_elements)
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#define NUM_TX_BUF_ELEMENTS DT_PROP(MCAN_DT_PATH, tx_buffer_elements)
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#ifdef CONFIG_CAN_STM32FD
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@ -1453,6 +1453,14 @@
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#define CAN_MCAN_TXEFA_EFAI CAN_MCAN_TXEFA_EFAI_MSK
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#endif /* CONFIG_CAN_STM32FD */
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/*************** Bit definition for CAN_MCAN_MRBA register *****************/
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#ifdef CONFIG_CAN_MCUX_MCAN
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/* Event FIFO Acknowledge Index */
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#define CAN_MCAN_MRBA_BA_POS (16U)
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#define CAN_MCAN_MRBA_BA_MSK (0xFFFFUL << CAN_MCAN_MRBA_BA_POS)
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#define CAN_MCAN_MRBA_BA CAN_MCAN_MRBA_BA_MSK
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#endif /* CONFIG_CAN_MCUX_MCAN */
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#ifdef CONFIG_CAN_STM32FD
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struct can_mcan_reg {
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volatile uint32_t crel; /* Core Release Register */
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@ -1553,6 +1561,10 @@ struct can_mcan_reg {
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volatile uint32_t txefc; /* Tx Event FIFO Configuration */
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volatile uint32_t txefs; /* Tx Event FIFO Status */
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volatile uint32_t txefa; /* Tx Event FIFO Acknowledge */
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#ifdef CONFIG_CAN_MCUX_MCAN
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volatile uint32_t res6[65]; /* Reserved (65) */
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volatile uint32_t mrba; /* Message RAM Base Address */
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#endif /* CONFIG_CAN_MCUX_MCAN */
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};
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#endif /* CONFIG_CAN_STM32FD */
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266
drivers/can/can_mcux_mcan.c
Normal file
266
drivers/can/can_mcux_mcan.c
Normal file
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@ -0,0 +1,266 @@
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/*
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* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <drivers/can.h>
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#include <drivers/clock_control.h>
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#include <logging/log.h>
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#include "can_mcan.h"
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LOG_MODULE_REGISTER(mcux_mcan, CONFIG_CAN_LOG_LEVEL);
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#define DT_DRV_COMPAT nxp_lpc_mcan
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struct mcux_mcan_config {
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struct can_mcan_config mcan;
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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void (*irq_config_func)(const struct device *dev);
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};
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struct mcux_mcan_data {
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struct can_mcan_data mcan;
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struct can_mcan_msg_sram msg_ram __nocache;
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};
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static int mcux_mcan_set_mode(const struct device *dev, enum can_mode mode)
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{
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const struct mcux_mcan_config *config = dev->config;
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return can_mcan_set_mode(&config->mcan, mode);
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}
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static int mcux_mcan_set_timing(const struct device *dev,
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const struct can_timing *timing,
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const struct can_timing *timing_data)
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{
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const struct mcux_mcan_config *config = dev->config;
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return can_mcan_set_timing(&config->mcan, timing, timing_data);
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}
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static int mcux_mcan_send(const struct device *dev, const struct zcan_frame *msg,
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k_timeout_t timeout, can_tx_callback_t callback,
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void *user_data)
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{
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const struct mcux_mcan_config *config = dev->config;
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struct mcux_mcan_data *data = dev->data;
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return can_mcan_send(&config->mcan, &data->mcan, &data->msg_ram,
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msg, timeout, callback, user_data);
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}
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static int mcux_mcan_add_rx_filter(const struct device *dev,
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can_rx_callback_t cb,
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void *user_data,
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const struct zcan_filter *filter)
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{
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struct mcux_mcan_data *data = dev->data;
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return can_mcan_add_rx_filter(&data->mcan, &data->msg_ram,
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cb, user_data, filter);
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}
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static void mcux_mcan_remove_rx_filter(const struct device *dev, int filter_id)
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{
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struct mcux_mcan_data *data = dev->data;
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can_mcan_remove_rx_filter(&data->mcan, &data->msg_ram, filter_id);
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}
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static enum can_state mcux_mcan_get_state(const struct device *dev,
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struct can_bus_err_cnt *err_cnt)
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{
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const struct mcux_mcan_config *config = dev->config;
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return can_mcan_get_state(&config->mcan, err_cnt);
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}
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static void mcux_mcan_set_state_change_callback(const struct device *dev,
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can_state_change_callback_t cb)
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{
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struct mcux_mcan_data *data = dev->data;
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data->mcan.state_change_cb = cb;
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}
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static int mcux_mcan_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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const struct mcux_mcan_config *config = dev->config;
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return clock_control_get_rate(config->clock_dev, config->clock_subsys,
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rate);
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}
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static void mcux_mcan_line_0_isr(const struct device *dev)
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{
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const struct mcux_mcan_config *config = dev->config;
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struct mcux_mcan_data *data = dev->data;
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can_mcan_line_0_isr(&config->mcan, &data->msg_ram, &data->mcan);
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}
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static void mcux_mcan_line_1_isr(const struct device *dev)
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{
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const struct mcux_mcan_config *config = dev->config;
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struct mcux_mcan_data *data = dev->data;
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can_mcan_line_1_isr(&config->mcan, &data->msg_ram, &data->mcan);
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}
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static int mcux_mcan_init(const struct device *dev)
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{
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const struct mcux_mcan_config *config = dev->config;
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struct mcux_mcan_data *data = dev->data;
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int err;
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err = clock_control_on(config->clock_dev, config->clock_subsys);
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if (err) {
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LOG_ERR("failed to enable clock (err %d)", err);
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return -EINVAL;
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}
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err = can_mcan_init(dev, &config->mcan, &data->msg_ram, &data->mcan);
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if (err) {
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LOG_ERR("failed to initialize mcan (err %d)", err);
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return err;
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}
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config->irq_config_func(dev);
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return 0;
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}
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static const struct can_driver_api mcux_mcan_driver_api = {
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.set_mode = mcux_mcan_set_mode,
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.set_timing = mcux_mcan_set_timing,
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.send = mcux_mcan_send,
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.add_rx_filter = mcux_mcan_add_rx_filter,
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.remove_rx_filter = mcux_mcan_remove_rx_filter,
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#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
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.recover = can_mcan_recover,
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#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
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.get_state = mcux_mcan_get_state,
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.set_state_change_callback = mcux_mcan_set_state_change_callback,
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.get_core_clock = mcux_mcan_get_core_clock,
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/*
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* MCUX MCAN timing limits are specified in the "Nominal bit timing and
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* prescaler register (NBTP)" table in the SoC reference manual.
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*
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* Note that the values here are the "physical" timing limits, whereas
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* the register field limits are physical values minus 1 (which is
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* handled by the register assignments in the common MCAN driver code).
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*/
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.timing_min = {
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.sjw = 1,
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.prop_seg = 0,
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.phase_seg1 = 1,
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.phase_seg2 = 1,
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.prescaler = 1
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},
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.timing_max = {
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.sjw = 128,
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.prop_seg = 0,
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.phase_seg1 = 256,
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.phase_seg2 = 128,
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.prescaler = 512,
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},
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#ifdef CONFIG_CAN_FD_MODE
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/*
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* MCUX MCAN data timing limits are specified in the "Data bit timing
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* and prescaler register (DBTP)" table in the SoC reference manual.
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*
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* Note that the values here are the "physical" timing limits, whereas
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* the register field limits are physical values minus 1 (which is
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* handled by the register assignments in the common MCAN driver code).
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*/
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.timing_min_data = {
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.sjw = 1,
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.prop_seg = 0,
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.phase_seg1 = 1,
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.phase_seg2 = 1,
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.prescaler = 1,
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},
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.timing_max_data = {
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.sjw = 16,
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.prop_seg = 0,
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.phase_seg1 = 16,
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.phase_seg2 = 16,
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.prescaler = 32,
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}
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#endif /* CONFIG_CAN_FD_MODE */
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};
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#ifdef CONFIG_CAN_FD_MODE
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#define MCUX_MCAN_MCAN_INIT(n) \
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{ \
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.can = (struct can_mcan_reg *)DT_INST_REG_ADDR(n), \
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.bus_speed = DT_INST_PROP(n, bus_speed), \
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.sjw = DT_INST_PROP(n, sjw), \
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.sample_point = DT_INST_PROP_OR(n, sample_point, 0), \
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.prop_ts1 = DT_INST_PROP_OR(n, prop_seg, 0) + \
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DT_INST_PROP_OR(n, phase_seg1, 0), \
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.ts2 = DT_INST_PROP_OR(n, phase_seg2, 0), \
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.bus_speed_data = DT_INST_PROP(n, bus_speed_data), \
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.sjw_data = DT_INST_PROP(n, sjw_data), \
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.sample_point_data = \
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DT_INST_PROP_OR(n, sample_point_data, 0), \
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.prop_ts1_data = DT_INST_PROP_OR(n, prop_seg_data, 0) + \
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DT_INST_PROP_OR(n, phase_seg1_data, 0), \
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.ts2_data = DT_INST_PROP_OR(n, phase_seg2_data, 0), \
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.tx_delay_comp_offset = \
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DT_INST_PROP(n, tx_delay_comp_offset) \
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}
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#else /* CONFIG_CAN_FD_MODE */
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#define MCUX_MCAN_MCAN_INIT(n) \
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{ \
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.can = (struct can_mcan_reg *)DT_INST_REG_ADDR(n), \
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.bus_speed = DT_INST_PROP(n, bus_speed), \
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.sjw = DT_INST_PROP(n, sjw), \
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.sample_point = DT_INST_PROP_OR(n, sample_point, 0), \
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.prop_ts1 = DT_INST_PROP_OR(n, prop_seg, 0) + \
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DT_INST_PROP_OR(n, phase_seg1, 0), \
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.ts2 = DT_INST_PROP_OR(n, phase_seg2, 0), \
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}
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#endif /* !CONFIG_CAN_FD_MODE */
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#define MCUX_MCAN_INIT(n) \
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static void mcux_mcan_irq_config_##n(const struct device *dev); \
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\
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static const struct mcux_mcan_config mcux_mcan_config_##n = { \
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.mcan = MCUX_MCAN_MCAN_INIT(n), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.clock_subsys = (clock_control_subsys_t) \
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DT_INST_CLOCKS_CELL(n, name), \
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.irq_config_func = mcux_mcan_irq_config_##n, \
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}; \
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\
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static struct mcux_mcan_data mcux_mcan_data_##n; \
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\
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DEVICE_DT_INST_DEFINE(n, &mcux_mcan_init, NULL, \
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&mcux_mcan_data_##n, \
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&mcux_mcan_config_##n, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&mcux_mcan_driver_api); \
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\
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static void mcux_mcan_irq_config_##n(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), \
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DT_INST_IRQ_BY_IDX(n, 0, priority), \
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mcux_mcan_line_0_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(n, 0, irq)); \
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\
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 1, irq), \
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DT_INST_IRQ_BY_IDX(n, 1, priority), \
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mcux_mcan_line_1_isr, \
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DEVICE_DT_INST_GET(n), 0); \
|
||||
irq_enable(DT_INST_IRQ_BY_IDX(n, 1, irq)); \
|
||||
}
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(MCUX_MCAN_INIT)
|
||||
Loading…
Add table
Add a link
Reference in a new issue