From 93c6b7413bcde665ce1e11729c16a33a68c056c1 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 31 May 2021 22:18:48 +0200 Subject: [PATCH] drivers: can: add NXP LPC MCAN front-end for the Bosch MCAN driver Add a NXP LPC MCAN-specific front-end for the generic Bosch MCAN driver. Signed-off-by: Henrik Brix Andersen --- drivers/can/CMakeLists.txt | 1 + drivers/can/Kconfig.mcux | 7 + drivers/can/can_mcan.c | 20 +++ drivers/can/can_mcan.h | 20 ++- drivers/can/can_mcan_int.h | 12 ++ drivers/can/can_mcux_mcan.c | 266 ++++++++++++++++++++++++++++++++++++ 6 files changed, 319 insertions(+), 7 deletions(-) create mode 100644 drivers/can/can_mcux_mcan.c diff --git a/drivers/can/CMakeLists.txt b/drivers/can/CMakeLists.txt index d4dd97f4b97..1553cc23ca8 100644 --- a/drivers/can/CMakeLists.txt +++ b/drivers/can/CMakeLists.txt @@ -1,6 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_library() +zephyr_sources_ifdef(CONFIG_CAN_MCUX_MCAN can_mcux_mcan.c) zephyr_library_sources_ifdef(CONFIG_CAN can_common.c) zephyr_library_sources_ifdef(CONFIG_CAN_LOOPBACK can_loopback.c) diff --git a/drivers/can/Kconfig.mcux b/drivers/can/Kconfig.mcux index 35fd32b3651..7d27ddc5aed 100644 --- a/drivers/can/Kconfig.mcux +++ b/drivers/can/Kconfig.mcux @@ -18,3 +18,10 @@ config CAN_MAX_FILTER range 1 64 if SOC_SERIES_IMX_RT help Defines maximum number of concurrent active RX filters + +config CAN_MCUX_MCAN + bool "MCUX MCAN driver" + depends on HAS_MCUX_MCAN && CLOCK_CONTROL + select CAN_MCAN + help + Enable support for mcux mcan driver. diff --git a/drivers/can/can_mcan.c b/drivers/can/can_mcan.c index 9927c07c89e..fdf935dcc9f 100644 --- a/drivers/can/can_mcan.c +++ b/drivers/can/can_mcan.c @@ -297,6 +297,24 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg, (can->crel & CAN_MCAN_CREL_DAY) >> CAN_MCAN_CREL_DAY_POS); #ifndef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_MCUX_MCAN + uint32_t mrba = (uint32_t)msg_ram & CAN_MCAN_MRBA_BA_MSK; + + can->mrba = mrba; + can->sidfc = (((uint32_t)msg_ram->std_filt - mrba) & CAN_MCAN_SIDFC_FLSSA_MSK) | + (ARRAY_SIZE(msg_ram->std_filt) << CAN_MCAN_SIDFC_LSS_POS); + can->xidfc = (((uint32_t)msg_ram->ext_filt - mrba) & CAN_MCAN_XIDFC_FLESA_MSK) | + (ARRAY_SIZE(msg_ram->ext_filt) << CAN_MCAN_XIDFC_LSS_POS); + can->rxf0c = (((uint32_t)msg_ram->rx_fifo0 - mrba) & CAN_MCAN_RXF0C_F0SA) | + (ARRAY_SIZE(msg_ram->rx_fifo0) << CAN_MCAN_RXF0C_F0S_POS); + can->rxf1c = (((uint32_t)msg_ram->rx_fifo1 - mrba) & CAN_MCAN_RXF1C_F1SA) | + (ARRAY_SIZE(msg_ram->rx_fifo1) << CAN_MCAN_RXF1C_F1S_POS); + can->rxbc = (((uint32_t)msg_ram->rx_buffer - mrba) & CAN_MCAN_RXBC_RBSA); + can->txefc = (((uint32_t)msg_ram->tx_event_fifo - mrba) & CAN_MCAN_TXEFC_EFSA_MSK) | + (ARRAY_SIZE(msg_ram->tx_event_fifo) << CAN_MCAN_TXEFC_EFS_POS); + can->txbc = (((uint32_t)msg_ram->tx_buffer - mrba) & CAN_MCAN_TXBC_TBSA_MSK) | + (ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS); +#else /* CONFIG_CAN_MCUX_MCAN */ can->sidfc = ((uint32_t)msg_ram->std_filt & CAN_MCAN_SIDFC_FLSSA_MSK) | (ARRAY_SIZE(msg_ram->std_filt) << CAN_MCAN_SIDFC_LSS_POS); can->xidfc = ((uint32_t)msg_ram->ext_filt & CAN_MCAN_XIDFC_FLESA_MSK) | @@ -311,6 +329,8 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg, CAN_MCAN_TXEFC_EFS_POS); can->txbc = ((uint32_t)msg_ram->tx_buffer & CAN_MCAN_TXBC_TBSA) | (ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS); +#endif /* !CONFIG_CAN_MCUX_MCAN */ + if (sizeof(msg_ram->tx_buffer[0].data) <= 24) { can->txesc = (sizeof(msg_ram->tx_buffer[0].data) - 8) / 4; } else { diff --git a/drivers/can/can_mcan.h b/drivers/can/can_mcan.h index e94573b42d2..068b167f843 100644 --- a/drivers/can/can_mcan.h +++ b/drivers/can/can_mcan.h @@ -8,14 +8,20 @@ #ifndef ZEPHYR_DRIVERS_CAN_MCAN_H_ #define ZEPHYR_DRIVERS_CAN_MCAN_H_ -#define NUM_STD_FILTER_ELEMENTS DT_PROP(DT_PATH(soc, can), std_filter_elements) -#define NUM_EXT_FILTER_ELEMENTS DT_PROP(DT_PATH(soc, can), ext_filter_elements) -#define NUM_RX_FIFO0_ELEMENTS DT_PROP(DT_PATH(soc, can), rx_fifo0_elements) -#define NUM_RX_FIFO1_ELEMENTS DT_PROP(DT_PATH(soc, can), rx_fifo0_elements) -#define NUM_RX_BUF_ELEMENTS DT_PROP(DT_PATH(soc, can), rx_buffer_elements) +#ifdef CONFIG_CAN_MCUX_MCAN +#define MCAN_DT_PATH DT_NODELABEL(can0) +#else +#define MCAN_DT_PATH DT_PATH(soc, can) +#endif + +#define NUM_STD_FILTER_ELEMENTS DT_PROP(MCAN_DT_PATH, std_filter_elements) +#define NUM_EXT_FILTER_ELEMENTS DT_PROP(MCAN_DT_PATH, ext_filter_elements) +#define NUM_RX_FIFO0_ELEMENTS DT_PROP(MCAN_DT_PATH, rx_fifo0_elements) +#define NUM_RX_FIFO1_ELEMENTS DT_PROP(MCAN_DT_PATH, rx_fifo0_elements) +#define NUM_RX_BUF_ELEMENTS DT_PROP(MCAN_DT_PATH, rx_buffer_elements) #define NUM_TX_EVENT_FIFO_ELEMENTS \ - DT_PROP(DT_PATH(soc, can), tx_event_fifo_elements) -#define NUM_TX_BUF_ELEMENTS DT_PROP(DT_PATH(soc, can), tx_buffer_elements) + DT_PROP(MCAN_DT_PATH, tx_event_fifo_elements) +#define NUM_TX_BUF_ELEMENTS DT_PROP(MCAN_DT_PATH, tx_buffer_elements) #ifdef CONFIG_CAN_STM32FD diff --git a/drivers/can/can_mcan_int.h b/drivers/can/can_mcan_int.h index e326294bd44..63d2ec06fa9 100644 --- a/drivers/can/can_mcan_int.h +++ b/drivers/can/can_mcan_int.h @@ -1453,6 +1453,14 @@ #define CAN_MCAN_TXEFA_EFAI CAN_MCAN_TXEFA_EFAI_MSK #endif /* CONFIG_CAN_STM32FD */ +/*************** Bit definition for CAN_MCAN_MRBA register *****************/ +#ifdef CONFIG_CAN_MCUX_MCAN +/* Event FIFO Acknowledge Index */ +#define CAN_MCAN_MRBA_BA_POS (16U) +#define CAN_MCAN_MRBA_BA_MSK (0xFFFFUL << CAN_MCAN_MRBA_BA_POS) +#define CAN_MCAN_MRBA_BA CAN_MCAN_MRBA_BA_MSK +#endif /* CONFIG_CAN_MCUX_MCAN */ + #ifdef CONFIG_CAN_STM32FD struct can_mcan_reg { volatile uint32_t crel; /* Core Release Register */ @@ -1553,6 +1561,10 @@ struct can_mcan_reg { volatile uint32_t txefc; /* Tx Event FIFO Configuration */ volatile uint32_t txefs; /* Tx Event FIFO Status */ volatile uint32_t txefa; /* Tx Event FIFO Acknowledge */ +#ifdef CONFIG_CAN_MCUX_MCAN + volatile uint32_t res6[65]; /* Reserved (65) */ + volatile uint32_t mrba; /* Message RAM Base Address */ +#endif /* CONFIG_CAN_MCUX_MCAN */ }; #endif /* CONFIG_CAN_STM32FD */ diff --git a/drivers/can/can_mcux_mcan.c b/drivers/can/can_mcux_mcan.c new file mode 100644 index 00000000000..60ee7f73dde --- /dev/null +++ b/drivers/can/can_mcux_mcan.c @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2021 Henrik Brix Andersen + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include "can_mcan.h" + +LOG_MODULE_REGISTER(mcux_mcan, CONFIG_CAN_LOG_LEVEL); + +#define DT_DRV_COMPAT nxp_lpc_mcan + +struct mcux_mcan_config { + struct can_mcan_config mcan; + const struct device *clock_dev; + clock_control_subsys_t clock_subsys; + void (*irq_config_func)(const struct device *dev); +}; + +struct mcux_mcan_data { + struct can_mcan_data mcan; + struct can_mcan_msg_sram msg_ram __nocache; +}; + +static int mcux_mcan_set_mode(const struct device *dev, enum can_mode mode) +{ + const struct mcux_mcan_config *config = dev->config; + + return can_mcan_set_mode(&config->mcan, mode); +} + +static int mcux_mcan_set_timing(const struct device *dev, + const struct can_timing *timing, + const struct can_timing *timing_data) +{ + const struct mcux_mcan_config *config = dev->config; + + return can_mcan_set_timing(&config->mcan, timing, timing_data); +} + +static int mcux_mcan_send(const struct device *dev, const struct zcan_frame *msg, + k_timeout_t timeout, can_tx_callback_t callback, + void *user_data) +{ + const struct mcux_mcan_config *config = dev->config; + struct mcux_mcan_data *data = dev->data; + + return can_mcan_send(&config->mcan, &data->mcan, &data->msg_ram, + msg, timeout, callback, user_data); +} + +static int mcux_mcan_add_rx_filter(const struct device *dev, + can_rx_callback_t cb, + void *user_data, + const struct zcan_filter *filter) +{ + struct mcux_mcan_data *data = dev->data; + + return can_mcan_add_rx_filter(&data->mcan, &data->msg_ram, + cb, user_data, filter); +} + +static void mcux_mcan_remove_rx_filter(const struct device *dev, int filter_id) +{ + struct mcux_mcan_data *data = dev->data; + + can_mcan_remove_rx_filter(&data->mcan, &data->msg_ram, filter_id); +} + +static enum can_state mcux_mcan_get_state(const struct device *dev, + struct can_bus_err_cnt *err_cnt) +{ + const struct mcux_mcan_config *config = dev->config; + + return can_mcan_get_state(&config->mcan, err_cnt); +} + +static void mcux_mcan_set_state_change_callback(const struct device *dev, + can_state_change_callback_t cb) +{ + struct mcux_mcan_data *data = dev->data; + + data->mcan.state_change_cb = cb; +} + +static int mcux_mcan_get_core_clock(const struct device *dev, uint32_t *rate) +{ + const struct mcux_mcan_config *config = dev->config; + + return clock_control_get_rate(config->clock_dev, config->clock_subsys, + rate); +} + +static void mcux_mcan_line_0_isr(const struct device *dev) +{ + const struct mcux_mcan_config *config = dev->config; + struct mcux_mcan_data *data = dev->data; + + can_mcan_line_0_isr(&config->mcan, &data->msg_ram, &data->mcan); +} + +static void mcux_mcan_line_1_isr(const struct device *dev) +{ + const struct mcux_mcan_config *config = dev->config; + struct mcux_mcan_data *data = dev->data; + + can_mcan_line_1_isr(&config->mcan, &data->msg_ram, &data->mcan); +} + +static int mcux_mcan_init(const struct device *dev) +{ + const struct mcux_mcan_config *config = dev->config; + struct mcux_mcan_data *data = dev->data; + int err; + + err = clock_control_on(config->clock_dev, config->clock_subsys); + if (err) { + LOG_ERR("failed to enable clock (err %d)", err); + return -EINVAL; + } + + err = can_mcan_init(dev, &config->mcan, &data->msg_ram, &data->mcan); + if (err) { + LOG_ERR("failed to initialize mcan (err %d)", err); + return err; + } + + config->irq_config_func(dev); + + return 0; +} + +static const struct can_driver_api mcux_mcan_driver_api = { + .set_mode = mcux_mcan_set_mode, + .set_timing = mcux_mcan_set_timing, + .send = mcux_mcan_send, + .add_rx_filter = mcux_mcan_add_rx_filter, + .remove_rx_filter = mcux_mcan_remove_rx_filter, +#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY + .recover = can_mcan_recover, +#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ + .get_state = mcux_mcan_get_state, + .set_state_change_callback = mcux_mcan_set_state_change_callback, + .get_core_clock = mcux_mcan_get_core_clock, + /* + * MCUX MCAN timing limits are specified in the "Nominal bit timing and + * prescaler register (NBTP)" table in the SoC reference manual. + * + * Note that the values here are the "physical" timing limits, whereas + * the register field limits are physical values minus 1 (which is + * handled by the register assignments in the common MCAN driver code). + */ + .timing_min = { + .sjw = 1, + .prop_seg = 0, + .phase_seg1 = 1, + .phase_seg2 = 1, + .prescaler = 1 + }, + .timing_max = { + .sjw = 128, + .prop_seg = 0, + .phase_seg1 = 256, + .phase_seg2 = 128, + .prescaler = 512, + }, +#ifdef CONFIG_CAN_FD_MODE + /* + * MCUX MCAN data timing limits are specified in the "Data bit timing + * and prescaler register (DBTP)" table in the SoC reference manual. + * + * Note that the values here are the "physical" timing limits, whereas + * the register field limits are physical values minus 1 (which is + * handled by the register assignments in the common MCAN driver code). + */ + .timing_min_data = { + .sjw = 1, + .prop_seg = 0, + .phase_seg1 = 1, + .phase_seg2 = 1, + .prescaler = 1, + }, + .timing_max_data = { + .sjw = 16, + .prop_seg = 0, + .phase_seg1 = 16, + .phase_seg2 = 16, + .prescaler = 32, + } +#endif /* CONFIG_CAN_FD_MODE */ +}; + +#ifdef CONFIG_CAN_FD_MODE +#define MCUX_MCAN_MCAN_INIT(n) \ + { \ + .can = (struct can_mcan_reg *)DT_INST_REG_ADDR(n), \ + .bus_speed = DT_INST_PROP(n, bus_speed), \ + .sjw = DT_INST_PROP(n, sjw), \ + .sample_point = DT_INST_PROP_OR(n, sample_point, 0), \ + .prop_ts1 = DT_INST_PROP_OR(n, prop_seg, 0) + \ + DT_INST_PROP_OR(n, phase_seg1, 0), \ + .ts2 = DT_INST_PROP_OR(n, phase_seg2, 0), \ + .bus_speed_data = DT_INST_PROP(n, bus_speed_data), \ + .sjw_data = DT_INST_PROP(n, sjw_data), \ + .sample_point_data = \ + DT_INST_PROP_OR(n, sample_point_data, 0), \ + .prop_ts1_data = DT_INST_PROP_OR(n, prop_seg_data, 0) + \ + DT_INST_PROP_OR(n, phase_seg1_data, 0), \ + .ts2_data = DT_INST_PROP_OR(n, phase_seg2_data, 0), \ + .tx_delay_comp_offset = \ + DT_INST_PROP(n, tx_delay_comp_offset) \ + } +#else /* CONFIG_CAN_FD_MODE */ +#define MCUX_MCAN_MCAN_INIT(n) \ + { \ + .can = (struct can_mcan_reg *)DT_INST_REG_ADDR(n), \ + .bus_speed = DT_INST_PROP(n, bus_speed), \ + .sjw = DT_INST_PROP(n, sjw), \ + .sample_point = DT_INST_PROP_OR(n, sample_point, 0), \ + .prop_ts1 = DT_INST_PROP_OR(n, prop_seg, 0) + \ + DT_INST_PROP_OR(n, phase_seg1, 0), \ + .ts2 = DT_INST_PROP_OR(n, phase_seg2, 0), \ + } +#endif /* !CONFIG_CAN_FD_MODE */ + +#define MCUX_MCAN_INIT(n) \ + static void mcux_mcan_irq_config_##n(const struct device *dev); \ + \ + static const struct mcux_mcan_config mcux_mcan_config_##n = { \ + .mcan = MCUX_MCAN_MCAN_INIT(n), \ + .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .clock_subsys = (clock_control_subsys_t) \ + DT_INST_CLOCKS_CELL(n, name), \ + .irq_config_func = mcux_mcan_irq_config_##n, \ + }; \ + \ + static struct mcux_mcan_data mcux_mcan_data_##n; \ + \ + DEVICE_DT_INST_DEFINE(n, &mcux_mcan_init, NULL, \ + &mcux_mcan_data_##n, \ + &mcux_mcan_config_##n, \ + POST_KERNEL, \ + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ + &mcux_mcan_driver_api); \ + \ + static void mcux_mcan_irq_config_##n(const struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), \ + DT_INST_IRQ_BY_IDX(n, 0, priority), \ + mcux_mcan_line_0_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQ_BY_IDX(n, 0, irq)); \ + \ + IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 1, irq), \ + DT_INST_IRQ_BY_IDX(n, 1, priority), \ + mcux_mcan_line_1_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQ_BY_IDX(n, 1, irq)); \ + } + +DT_INST_FOREACH_STATUS_OKAY(MCUX_MCAN_INIT)