From 917bc51d2dc7be16bf29efa16728f8beab1de3d3 Mon Sep 17 00:00:00 2001
From: Daniel Leung <daniel.leung@intel.com>
Date: Mon, 19 May 2025 14:15:47 -0700
Subject: [PATCH] xtensa: gdbstub: add arch_gdb_post_memory_write()

This adds arch_gdb_post_memory_write() to deal with caching
after GDB writing to memory.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
---
 arch/xtensa/core/gdbstub.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/xtensa/core/gdbstub.c b/arch/xtensa/core/gdbstub.c
index 5ce707bd114..52f1349eebe 100644
--- a/arch/xtensa/core/gdbstub.c
+++ b/arch/xtensa/core/gdbstub.c
@@ -7,6 +7,7 @@
 #include <zephyr/kernel.h>
 #include <kernel_internal.h>
 #include <zephyr/toolchain.h>
+#include <zephyr/arch/xtensa/cache.h>
 #include <zephyr/debug/gdbstub.h>
 
 #include <xtensa_asm2_context.h>
@@ -987,3 +988,35 @@ void arch_gdb_init(void)
 	 */
 	__asm__ volatile ("_break.n 0");
 }
+
+void arch_gdb_post_memory_write(uintptr_t addr, size_t len, uint8_t align)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(len);
+	ARG_UNUSED(align);
+
+#if defined(CONFIG_ICACHE) && defined(CONFIG_DCACHE)
+	/*
+	 * Note that a GDB memory write can write to code memory to
+	 * insert breakpoints. We need to deal with this here so
+	 * that the instruction cache can actually see the modified
+	 * instructions.
+	 *
+	 * According to the ISA manual, after writing the instructions:
+	 * 1. Flush the data cache so the modified instructions are
+	 *    in the main memory.
+	 * 2. Do ISYNC or MEMW or both (depending on which part of
+	 *    manual you are reading).
+	 * 3. Invalidate the instruction cache corresponding to
+	 *    the modified memory.
+	 * 4. Do another ISYNC.
+	 */
+	arch_dcache_flush_range(addr, len);
+
+	__asm__ volatile("isync; memw");
+
+	arch_icache_invd_range(addr, len);
+
+	__asm__ volatile("isync");
+#endif /* CONFIG_ICACHE && CONFIG_DCACHE */
+}