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drivers: pinctrl: update lpc pin control implementation to use offsets

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update pin control implementation to use offsets for pin registers
instead of pin/port combination, to permit additional flexibility for
lpc devices with non contiguous register layouts. Update LPC55s69 pin
control names to align with newly generated pin control header.

This change also requires an update to the NXP HAL to use the new pin
control headers with offsets.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-04-12 12:25:20 -05:00 • committed by David Leach
commit 916c059f3d
3 changed files with 10 additions and 11 deletions
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4
boards/arm/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi
View file

@ -66,8 +66,8 @@
pinmux_sctimer_default: pinmux_sctimer_default { pinmux_sctimer_default: pinmux_sctimer_default {
group0 { group0 {
pinmux = <SCT02_PIO0_15>, pinmux = <SCT0_OUT2_PIO0_15>,
<SCT00_PIO1_4>; <SCT0_OUT0_PIO1_4>;
slew-rate = "standard"; slew-rate = "standard";
}; };
}; };

15
drivers/pinctrl/pinctrl_lpc_iocon.c
View file

@ -7,25 +7,24 @@
#include <drivers/pinctrl.h> #include <drivers/pinctrl.h>
#include <fsl_clock.h> #include <fsl_clock.h>
#define PORT(mux) (((mux) & 0xC0000000) >> 30) #define OFFSET(mux) (((mux) & 0xFFF00000) >> 20)
#define PIN(mux) (((mux) & 0x3F000000) >> 24) #define TYPE(mux) (((mux) & 0xC0000) >> 18)
#define TYPE(mux) (((mux) & 0xC00000) >> 22)
#define IOCON_TYPE_D 0x0 #define IOCON_TYPE_D 0x0
#define IOCON_TYPE_I 0x1 #define IOCON_TYPE_I 0x1
#define IOCON_TYPE_A 0x2 #define IOCON_TYPE_A 0x2
static IOCON_Type *iocon = (IOCON_Type *)DT_REG_ADDR(DT_NODELABEL(iocon)); static volatile uint32_t *iocon =
(volatile uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon));
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg) uintptr_t reg)
{ {
for (uint8_t i = 0; i < pin_cnt; i++) { for (uint8_t i = 0; i < pin_cnt; i++) {
/* Check if this is an analog or i2c type pin */
uint32_t pin_mux = pins[i]; uint32_t pin_mux = pins[i];
uint32_t port = PORT(pin_mux); uint32_t offset = OFFSET(pin_mux);
uint32_t pin = PIN(pin_mux);
/* Check if this is an analog or i2c type pin */
switch (TYPE(pin_mux)) { switch (TYPE(pin_mux)) {
case IOCON_TYPE_D: case IOCON_TYPE_D:
pin_mux &= Z_PINCTRL_IOCON_D_PIN_MASK; pin_mux &= Z_PINCTRL_IOCON_D_PIN_MASK;
@ -41,7 +40,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
assert(TYPE(pin_mux <= IOCON_TYPE_A)); assert(TYPE(pin_mux <= IOCON_TYPE_A));
} }
/* Set pinmux */ /* Set pinmux */
iocon->PIO[port][pin] = pin_mux; *(iocon + offset) = pin_mux;
} }
return 0; return 0;
} }

2
west.yml
View file

@ -101,7 +101,7 @@ manifest:
groups: groups:
- hal - hal
- name: hal_nxp - name: hal_nxp
revision: ca1610119ca147b2cd1b875238881e4abb805297 revision: 46be8173d2453b16c617b555f96c59d62920a290
path: modules/hal/nxp path: modules/hal/nxp
groups: groups:
- hal - hal