From 916c059f3d45b1425822ec89200c6507577a09e9 Mon Sep 17 00:00:00 2001
From: Daniel DeGrasse <daniel.degrasse@nxp.com>
Date: Tue, 12 Apr 2022 12:25:20 -0500
Subject: [PATCH] drivers: pinctrl: update lpc pin control implementation to
 use offsets

update pin control implementation to use offsets for pin registers
instead of pin/port combination, to permit additional flexibility for
lpc devices with non contiguous register layouts. Update LPC55s69 pin
control names to align with newly generated pin control header.

This change also requires an update to the NXP HAL to use the new pin
control headers with offsets.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
---
 .../lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi  |  4 ++--
 drivers/pinctrl/pinctrl_lpc_iocon.c               | 15 +++++++--------
 west.yml                                          |  2 +-
 3 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi b/boards/arm/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi
index 27d4c6f1e91..42033dd39ed 100644
--- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi
+++ b/boards/arm/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi
@@ -66,8 +66,8 @@
 
 	pinmux_sctimer_default: pinmux_sctimer_default {
 		group0 {
-			pinmux = <SCT02_PIO0_15>,
-				<SCT00_PIO1_4>;
+			pinmux = <SCT0_OUT2_PIO0_15>,
+				<SCT0_OUT0_PIO1_4>;
 			slew-rate = "standard";
 		};
 	};
diff --git a/drivers/pinctrl/pinctrl_lpc_iocon.c b/drivers/pinctrl/pinctrl_lpc_iocon.c
index 33235717874..e4a287a370c 100644
--- a/drivers/pinctrl/pinctrl_lpc_iocon.c
+++ b/drivers/pinctrl/pinctrl_lpc_iocon.c
@@ -7,25 +7,24 @@
 #include <drivers/pinctrl.h>
 #include <fsl_clock.h>
 
-#define PORT(mux) (((mux) & 0xC0000000) >> 30)
-#define PIN(mux) (((mux) & 0x3F000000) >> 24)
-#define TYPE(mux) (((mux) & 0xC00000) >> 22)
+#define OFFSET(mux) (((mux) & 0xFFF00000) >> 20)
+#define TYPE(mux) (((mux) & 0xC0000) >> 18)
 
 #define IOCON_TYPE_D 0x0
 #define IOCON_TYPE_I 0x1
 #define IOCON_TYPE_A 0x2
 
-static IOCON_Type *iocon = (IOCON_Type *)DT_REG_ADDR(DT_NODELABEL(iocon));
+static volatile uint32_t *iocon =
+	(volatile uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon));
 
 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			   uintptr_t reg)
 {
 	for (uint8_t i = 0; i < pin_cnt; i++) {
-		/* Check if this is an analog or i2c type pin */
 		uint32_t pin_mux = pins[i];
-		uint32_t port = PORT(pin_mux);
-		uint32_t pin = PIN(pin_mux);
+		uint32_t offset = OFFSET(pin_mux);
 
+		/* Check if this is an analog or i2c type pin */
 		switch (TYPE(pin_mux)) {
 		case IOCON_TYPE_D:
 			pin_mux &= Z_PINCTRL_IOCON_D_PIN_MASK;
@@ -41,7 +40,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			assert(TYPE(pin_mux <= IOCON_TYPE_A));
 		}
 		/* Set pinmux */
-		iocon->PIO[port][pin] = pin_mux;
+		*(iocon + offset) = pin_mux;
 	}
 	return 0;
 }
diff --git a/west.yml b/west.yml
index 6bd1f91b2e7..9e61af807e0 100644
--- a/west.yml
+++ b/west.yml
@@ -101,7 +101,7 @@ manifest:
       groups:
         - hal
     - name: hal_nxp
-      revision: ca1610119ca147b2cd1b875238881e4abb805297
+      revision: 46be8173d2453b16c617b555f96c59d62920a290
       path: modules/hal/nxp
       groups:
         - hal