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soc: riscv32: Use same clock freq for both rv32m1 cores

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Both the ri5cy and zero-riscy cores in the rv32m1 soc use the same
source clock, so we don't need to conditionalize
SYS_CLOCK_HW_CYCLES_PER_SEC on the ri5cy core.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm 2018-12-02 18:41:38 -06:00 • committed by Kumar Gala
commit 8fa5353bd2
1 changed files with 1 additions and 1 deletions
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soc/riscv32/openisa_rv32m1/Kconfig.defconfig
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@ -81,7 +81,7 @@ config RISCV32_RV32M1_VECTOR_SIZE
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 8000000 if SOC_OPENISA_RV32M1_RI5CY # SIRC at 8MHz
default 8000000
if MULTI_LEVEL_INTERRUPTS