soc: riscv32: Use same clock freq for both rv32m1 cores
Both the ri5cy and zero-riscy cores in the rv32m1 soc use the same source clock, so we don't need to conditionalize SYS_CLOCK_HW_CYCLES_PER_SEC on the ri5cy core. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
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@ -81,7 +81,7 @@ config RISCV32_RV32M1_VECTOR_SIZE
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default 8000000 if SOC_OPENISA_RV32M1_RI5CY # SIRC at 8MHz
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default 8000000
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if MULTI_LEVEL_INTERRUPTS
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