From 8fa5353bd2bb0975b638d95d1636b9bfe41edb62 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Sun, 2 Dec 2018 18:41:38 -0600 Subject: [PATCH] soc: riscv32: Use same clock freq for both rv32m1 cores Both the ri5cy and zero-riscy cores in the rv32m1 soc use the same source clock, so we don't need to conditionalize SYS_CLOCK_HW_CYCLES_PER_SEC on the ri5cy core. Signed-off-by: Maureen Helm --- soc/riscv32/openisa_rv32m1/Kconfig.defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/riscv32/openisa_rv32m1/Kconfig.defconfig b/soc/riscv32/openisa_rv32m1/Kconfig.defconfig index 3b35faa638c..07dd337061e 100644 --- a/soc/riscv32/openisa_rv32m1/Kconfig.defconfig +++ b/soc/riscv32/openisa_rv32m1/Kconfig.defconfig @@ -81,7 +81,7 @@ config RISCV32_RV32M1_VECTOR_SIZE config SYS_CLOCK_HW_CYCLES_PER_SEC int - default 8000000 if SOC_OPENISA_RV32M1_RI5CY # SIRC at 8MHz + default 8000000 if MULTI_LEVEL_INTERRUPTS